Irregular LDPC Bit-Flipping Restart for Decoder Stagnation
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Solution Overview
Problem
Irregular low-density parity-check (LDPC) codes in non-volatile memory devices face challenges in decoding performance due to their sparse structure, leading to slow convergence and high error vulnerability, especially for variable nodes with small column weights, which affects data reliability in NAND flash memory systems.
Innovation Solution
An error mitigation scheme (EMS) is introduced that involves a bit-flipping algorithm, where if no bits are flipped during an iteration and the syndrome is non-zero, a bit with the smallest column weight connected to unsatisfied check nodes is flipped, and the syndrome is recalculated, helping to dislodge the algorithm from local minima and improve decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit-flipping algorithm is used for decoding irregular LDPC codes, then the decoding process can be implemented, but the algorithm may get stuck in local minima resulting in slow convergence and high error vulnerability
Solution Approach 1:
The patent applies preliminary action by proactively flipping bits at positions corresponding to variable nodes with smallest column weights that are connected to unsatisfied check nodes, before the algorithm can get permanently stuck in a local minimum. This preventive flipping action disrupts the stagnation and redirects the decoding process toward the correct solution, thereby improving both reliability and convergence speed.
Solution Approach 2:
The patent changes the decoding parameter by dynamically selecting which bits to flip based on column weight values and check node satisfaction status. Instead of uniform random flipping or fixed-pattern flipping, the algorithm adapts its flipping strategy by identifying variable nodes with smallest column weights connected to unsatisfied check nodes, thereby optimizing the decoding path and resolving the contradiction between reliability and convergence speed.
2Adaptability or versatility
If variable nodes with small column weights are present in irregular LDPC codes, then the code structure provides design flexibility, but these nodes are more vulnerable to errors and cause slow convergence
Solution Approach 1:
The patent applies local quality by treating variable nodes with small column weights differently from other nodes. Specifically, the algorithm identifies and prioritizes flipping operations at these vulnerable nodes when they are connected to unsatisfied check nodes. This localized attention to problematic nodes improves their error vulnerability without changing the overall irregular LDPC code structure, thereby maintaining design flexibility while enhancing reliability.
Solution Approach 2:
The patent effectively creates a corrected version of the codeword by flipping bits at strategically selected positions. When the original decoding path fails due to errors at vulnerable nodes, the algorithm generates a modified codeword version with corrected bits at critical positions, allowing the decoding process to continue from a more accurate state and achieve reliable convergence.
3Reliability
If no bits are flipped during an iteration but the syndrome is non-zero, then the algorithm has stalled, but continuing the same iteration pattern will not resolve the error
Solution Approach 1:
The patent applies preliminary action by proactively flipping bits at positions corresponding to variable nodes with smallest column weights that are connected to unsatisfied check nodes, before the algorithm can get permanently stuck in a local minimum. This preventive flipping action disrupts the stagnation and redirects the decoding process toward the correct solution, thereby improving both reliability and convergence speed.
Solution Approach 2:
The patent uses feedback by monitoring the syndrome value and the number of bit flips in each iteration. When the syndrome remains non-zero and no bits are flipped (indicating stagnation), the algorithm receives feedback that the current decoding path is stuck, and automatically adjusts its strategy by forcing a flip at a strategically selected variable node. This feedback-driven adaptation resolves the contradiction between error correction capability and decoding time.
Data Source
AI summary
Disclosed are devices, systems and methods for improving a bit-flipping algorithm for an irregular LDPC code in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated from an irregular low-density parity-check code, performing a first iteration of a bit-flipping algorithm on the noisy codeword, computing a first syndrome based on an output codeword of the first iteration, determining that the first syndrome comprises a non-zero vector and no bits of the noisy codeword were flipped during the first iteration of the bit-flipping algorithm, flipping, based on the determining, at least one bit of the output codeword, the at least one bit corresponding to a variable node of the plurality of variable nodes with a smallest column weight connected to one or more unsatisfied check nodes of the plurality of check nodes, and computing, subsequent to the flipping, a second syndrome.