LDPC Bit-Group Interleaver for 256-Symbol Burst-Error Mitigation
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 3/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order for effective distribution of burst errors, and a modulator performing 256-symbol mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (e.g., 45 groups of 360 bits each) and applies permutation interleaving at the bit group level. This segmentation allows burst errors to be distributed across different bit groups rather than concentrated in one location, thereby improving error distribution and system reliability without requiring complex per-bit interleaving
Solution Approach 2:
The patent optimizes the interleaver design by specifically matching the bit group size (360 bits) to the parallel factor of the LDPC coder and designing a permutation order tailored for 256-symbol mapping. These parameter optimizations enable effective burst error distribution while maintaining computational efficiency and system performance
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance is improved, but the device complexity increases
Solution Approach 1:
The patent designs a universal bit interleaver structure that works effectively for LDPC codes with length 16200 and code rate 3/15 combined with 256-symbol mapping. By establishing a standardized permutation order and bit group organization, the same interleaver design can be applied across different implementations without requiring custom designs for each specific parameter combination, thereby reducing overall system complexity
3Reliability
If burst errors are distributed via bit-by-bit interleaving, then performance is maintained, but the processing complexity and time increase
Solution Approach 1:
By performing interleaving at the bit group level (360 bits per group) rather than individual bit level, the patent reduces the number of interleaving operations from 16200 individual bits to 45 bit groups. This segmentation approach maintains effective error distribution while significantly reducing processing time and computational complexity
Solution Approach 2:
The patent combines multiple bits into bit groups of 360 bits each, which corresponds to the parallel factor of the LDPC coder. By merging bits into groups and applying a single permutation operation per group, the system achieves efficient error distribution with reduced processing overhead compared to individual bit interleving
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.