LDPC Bit-Group Interleaving for 4096-Point Data Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data transmission using LDPC codes faces challenges in maintaining excellent communication quality, particularly in ensuring high error correction capabilities and minimizing error floor phenomena in decoding characteristics.
Innovation Solution
A data processing device and method that performs LDPC encoding with a specific parity check matrix, group-wise interleaving, and mapping to 4096 signal points, utilizing a parity check matrix with a predetermined structure to enhance communication quality by optimizing bit group interleaving and decoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC encoding is performed with increased code length to approach Shannon limit, then error correction capability is improved, but system complexity and processing overhead increase
Solution Approach 1:
The patent applies segmentation by dividing the LDPC code into multiple bit groups (e.g., 360 bits per group) and performing group-wise interleaving. This segmentation allows the system to achieve excellent error correction capability near the Shannon limit while managing complexity through structured, modular processing of code segments rather than treating the entire code block monolithically.
Solution Approach 2:
The patent utilizes parameter changes by employing specific LDPC code configurations with predetermined code lengths (e.g., 64800 bits) and encoding rates (e.g., 6/15, 7/15), along with specific interleaving patterns. These optimized parameters enable the system to operate near the Shannon limit with improved reliability while maintaining manageable complexity through standardized parameter sets.
2Reliability
If group-wise interleaving is applied to optimize decoding characteristics, then error floor phenomenon is reduced, but processing time and computational load increase
Solution Approach 1:
The patent applies preliminary action by performing group-wise interleaving at the encoding stage with predetermined patterns (e.g., specific permutation sequences for bit groups). This preliminary arrangement of bits in optimized groups reduces the error floor phenomenon in decoding characteristics, and the structured nature of this preliminary action facilitates efficient processing during decoding, thereby reducing overall processing time despite the additional initial processing.
3Productivity
If mapping to 4096 signal points is implemented to enhance modulation capability, then data transmission efficiency is improved, but sensitivity to channel noise and errors increases
Solution Approach 1:
The patent applies segmentation by mapping LDPC code bits to 4096 signal points (12 bits per symbol) in a structured manner with specific bit group assignments. This segmentation of the modulation process, combined with the previously applied group-wise interleaving, allows the system to achieve high data transmission efficiency while the structured organization helps manage noise sensitivity through systematic error correction capabilities.
Data Source
AI summary
The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 64800 bits and an encoding rate r is 6/15, 7/15, 8/15, or 9/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.