LDPC Bit-Group Interleaving for 64-Symbol Burst Error Resilience
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 2/15, using 64-symbol mapping, which interleaves the LDPC codeword on a bit group basis according to a specific permutation order, effectively distributing burst errors and improving error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but performance degrades rapidly due to burst errors in digital broadcast channels
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (each containing 360 bits) and applies permutation interleaving at the bit group level. This segmentation approach distributes burst errors across different bit groups while maintaining a manageable interleaver structure that balances performance improvement with implementation complexity
Solution Approach 2:
The patent optimizes the interleaver by specifically designing the permutation order and bit group size (360 bits) to match the LDPC code parameters (64800 length, 2/15 code rate) and modulation scheme (64-QAM). This parameter optimization resolves the contradiction by tailoring the interleaver structure to the specific system configuration, achieving better error correction performance without excessive complexity
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error correction performance improves, but the adaptability to different system configurations decreases
Solution Approach 1:
The patent achieves optimized performance for specific parameters (64800-length LDPC, 2/15 code rate, 64-QAM) through carefully designed permutation orders and bit group configurations. While this optimization targets specific parameters, the fundamental interleaving structure remains adaptable to different configurations by adjusting the permutation sequence and bit group size to match the desired code and modulation parameters
3Reliability
If burst errors are distributed through bit-by-bit interleaving, then performance degradation is reduced, but the computational complexity and processing overhead increase
Solution Approach 1:
The patent reduces processing complexity by performing interleaving at the bit group level (360 bits per group) rather than individual bit level. This segmentation approach effectively distributes burst errors across bit groups while significantly reducing the computational burden and memory requirements compared to full bit-by-bit interleaving
Solution Approach 2:
The patent changes the interleaving dimension from individual bits to bit groups, effectively moving from a fine-grained to a coarse-grained approach. This dimensional change maintains the error distribution benefit while reducing processing complexity by operating on larger units of data
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.