LDPC Bit Group Interleaver for 1024-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 3/15, using 1024-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, effectively distributing burst errors by employing a specific permutation order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups, where each bit group contains a specific number of bits (e.g., 360 bits). This segmentation allows the interleaver to operate on bit groups rather than individual bits, effectively distributing burst errors across different bit groups while maintaining the overall structure needed for bandwidth-efficient transmission.
Solution Approach 2:
The patent introduces a new dimension of interleaving by operating on bit groups as units rather than individual bits. This group-based approach adds a structural layer to the interleaving process, enabling better error distribution while preserving the bandwidth efficiency of the underlying BICM system.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then excellent performance can be achieved, but the device complexity increases due to the need for optimization across multiple parameters
Solution Approach 1:
The patent employs parameter changes by adjusting the bit group size and permutation patterns based on specific modulation orders (e.g., 1024-QAM) and LDPC code parameters (length 64800, code rate 3/15). This allows the interleaver to be optimized for particular system configurations while maintaining a relatively simple group-based structure that doesn't excessively increase complexity.
Solution Approach 2:
The patent applies local quality by using different permutation patterns for different bit groups within the same codeword. Each bit group can be interleaved with a pattern suited to its specific position and the overall error distribution requirements, achieving high performance without requiring a completely unique design for each parameter combination.
3Reliability
If burst errors are distributed via bit-by-bit interleaving, then error correction performance is maintained, but the interleaving process becomes computationally intensive and complex
Solution Approach 1:
By segmenting the codeword into bit groups and performing interleaving at the group level rather than bit level, the patent reduces the computational complexity of the interleaving process. The segmentation allows errors to be distributed effectively while requiring fewer computational operations compared to true bit-by-bit interleaving.
Solution Approach 2:
The bit group acts as an intermediary between individual bits and the overall codeword structure. This intermediary structure simplifies the interleaving process by providing a manageable unit size that balances error distribution effectiveness with computational feasibility, avoiding the complexity of direct bit-by-bit manipulation.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.