LDPC Bit-Group Interleaver for Burst-Error-Resilient 4096-QAM

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 4/15, using 4096-symbol mapping, is designed to effectively distribute burst errors by interleaving LDPC codewords on a bit group basis, with a specific permutation order and memory structures for efficient error correction and modulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a bit-by-bit interleaver is used in BICM systems, then the system can provide high-level flexibility and bandwidth efficiency, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels

Engineering Contradiction:
ImproveflexibilityVSAvoidperformance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the LDPC codeword into multiple bit groups (e.g., 180 bit groups of 360 bits each) and applies bit-group-based interleaving within each group. This segmentation allows the system to maintain flexibility while effectively distributing burst errors across different groups, preventing concentrated error patterns that would degrade performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different interleaving strategies to different parts of the codeword structure. Specifically, it uses bit-group-based interleaving with specific permutation orders (such as the provided interleaving sequence) for different bit groups, optimizing error distribution locally while maintaining overall system flexibility.

Inventive Principle:
Principle #3Local quality

2Device complexity

If a conventional bit interleaver is used, then the system structure remains simple, but burst errors are not effectively distributed leading to performance degradation

Engineering Contradiction:
ImprovestructureVSAvoiderror distribution
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies preliminary bit-group-based interleaving to the LDPC codeword before modulation. The specific permutation order is pre-calculated and applied to distribute burst errors before they can concentrate during transmission, maintaining simple system structure while improving error distribution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a new dimension to the interleaving process by operating at the bit-group level rather than individual bit level. This dimensional change allows effective burst error distribution while maintaining computational simplicity and avoiding complex system architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If the interleaver is optimized for specific modulation order and code parameters, then performance is improved, but the system loses flexibility in adapting to different broadcasting standards

Engineering Contradiction:
ImproveperformanceVSAvoidflexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent designs a universal bit-group-based interleaver structure that can be applied to different LDPC code rates and modulation schemes. The interleaving framework supports various code rates (e.g., 4/15) and modulation orders (e.g., 4096-QAM) through parameter configuration rather than structural changes, maintaining both performance and flexibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent optimizes performance by changing parameters such as the number of bit groups (180 groups), group size (360 bits), and permutation sequences based on specific code rates and modulation orders. These parameter adjustments allow the same interleaver structure to adapt to different broadcasting standards and requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11646752B2Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 4096-symbol mapping, and bit interleaving method using same
Publication Date: 2023.05.09 ELECTRONICS & TELECOMM RES INST
  • US11646752B2 patent drawing
  • US11646752B2 patent drawing
  • US11646752B2 patent drawing

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.