LDPC Bit-Group Interleaver for 4096-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 3/15, using 4096-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, and integrated into a BICM device for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (each containing 360 bits) and applies separate permutation operations to each group. This segmentation allows the interleaver to effectively distribute burst errors across different groups while maintaining a manageable structure that doesn't require complex overall redesign
Solution Approach 2:
The patent optimizes the permutation order parameters specifically for 4096-QAM modulation and LDPC codes with length 64800 and code rate 3/15. By tuning these parameters to match the specific system configuration, the interleaver achieves optimal error distribution performance without requiring complex adaptive mechanisms
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error distribution performance improves, but the system loses flexibility
Solution Approach 1:
The patent employs parameterized permutation orders that can be configured for different modulation orders and LDPC code parameters. The general structure remains the same, but the specific permutation sequence parameters are adjusted based on the operating conditions, allowing optimization for each scenario without redesigning the entire interleaver architecture
3Adaptability or versatility
If a general-purpose bit interleaver is used, then the system maintains flexibility for different configurations, but it cannot effectively distribute burst errors for specific modulation and code parameters
Solution Approach 1:
The patent segments the codeword into bit groups and applies permutation operations that can be independently configured. This segmentation provides a flexible framework where the same basic structure can be adapted to different modulation orders and code rates by simply changing the permutation parameters for each group, rather than requiring a completely different interleaver design
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.