LDPC Bit-Group Interleaving for 64-Symbol Burst Error Dispersion

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 4/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order for effective distribution of burst errors, and integrated with a modulator for 64-symbol mapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a bit-by-bit interleaver is used in BICM systems, then the system can provide high-level flexibility and bandwidth efficiency, but burst errors occurring in the channel cause rapid performance degradation

Engineering Contradiction:

ImproveflexibilityVSAvoidperformance

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the codeword into multiple bit groups (e.g., 45 bit groups of 360 bits each for a 16200-length LDPC codeword) and applies permutation-based interleaving at the bit group level. This segmentation approach maintains the flexibility of BICM while distributing burst errors across different bit groups, preventing concentrated error patterns that would degrade performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of interleaving by applying permutation orders to bit group indices rather than individual bits. This dimensional shift from bit-level to bit-group-level interleaving provides a coarser granularity that effectively disperses burst errors while maintaining system flexibility for various modulation schemes and code rates.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the bit interleaver is optimized for specific modulation order and code parameters, then performance is maintained, but the device complexity increases

Engineering Contradiction:

ImproveperformanceVSAvoidinterleaver design

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent optimizes performance by changing key parameters of the interleaver including the permutation order sequence, bit group size (parallel factor), and interleaving depth. These parameter adjustments are tailored to specific modulation orders (e.g., 64-QAM) and LDPC code parameters (length 16200, code rate 4/15), achieving high performance while keeping the interleaver structure relatively simple through parameter tuning rather than structural complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11588502B2Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 64-symbol mapping, and bit interleaving method using same

Publication Date: 2023.02.21 ELECTRONICS & TELECOMM RES INST

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.