LDPC Bit-Group Interleaving for Broadcast Decoding Reliability

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Solution Overview

Problem

There is a need for improved decoding and receiving performance in digital broadcasting services, particularly in high quality digital televisions and portable multimedia players, due to the increasing demand for efficient methods to support various receiving methods of digital broadcasting services.

Innovation Solution

A transmitting apparatus and method that uses an LDPC codeword encoder, interleaver, and modulator to map bits from a predetermined bit group of a low density parity check (LDPC) codeword onto modulation symbols, incorporating a parity interleaver, group interleaver, and block interleaver to enhance decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC encoding and modulation mapping is used, then the system supports basic digital broadcasting services, but decoding and receiving performance is insufficient for high quality digital televisions and portable multimedia players

Engineering Contradiction:
Improvedecoding and receiving performanceVSAvoidinterleaving structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the LDPC codeword into multiple bit groups and processes them through different interleaving stages (parity interleaver, group interleaver, block interleaver). This segmentation allows the system to achieve improved decoding performance by distributing bits across multiple processing stages, while managing complexity through modular architecture where each stage handles a specific aspect of the interleaving process

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces multiple dimensions of interleaving processing: bit-level parity interleaving, group-level reordering, and block-level column-wise writing. By adding these dimensional layers of processing, the system enhances decoding performance through more comprehensive bit distribution across modulation symbols, transforming a single-dimension problem into a multi-dimensional solution space

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If bit groups are interleaved to improve decoding performance, then receiving reliability is enhanced, but the processing complexity and device structure increase

Engineering Contradiction:
Improvereceiving performanceVSAvoidinterleaver structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interleaver is segmented into three distinct functional modules: parity interleaver for bit-level processing, group interleaver for group-level reordering, and block interleaver for block-level column-wise operations. This segmentation enables the system to achieve comprehensive interleaving performance while managing complexity through clear separation of concerns, where each module has a specific, well-defined function

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The parity interleaver performs preliminary bit reordering within each bit group before the codeword is divided into groups for subsequent processing. This preliminary action ensures that parity bits are properly distributed at the bit level before group-level and block-level interleaving occurs, establishing a foundation for improved decoding performance that carries through all subsequent processing stages

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10312941B2Transmitting apparatus and interleaving method thereof
Publication Date: 2019.06.04 SAMSUNG ELECTRONICS CO LTD
  • US10312941B2 patent drawing
  • US10312941B2 patent drawing
  • US10312941B2 patent drawing

AI summary

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.