LDPC Bit Group Interleaving for Robust Symbol Mapping
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Solution Overview
Problem
There is a need for improved methods to support high decoding and receiving performance in digital broadcasting services, particularly in the context of high-quality digital televisions and portable multimedia devices, where existing technologies fall short in providing efficient data transmission and reception.
Innovation Solution
A transmitting apparatus and method that employs LDPC encoding, interleaving, and modulation to map bits from a predetermined bit group of a low-density parity-check (LDPC) codeword onto modulation symbols, utilizing a parity interleaver, group interleaver, and block interleaver to enhance decoding and receiving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC encoding is used to improve decoding performance, then receiving performance is improved, but device complexity increases due to the need for additional encoding and interleaving components
Solution Approach 1:
The transmitting apparatus segments the LDPC codeword into multiple bit groups, which are then processed independently through the interleaver. This segmentation allows the complex LDPC encoding to be broken down into manageable portions that can be interleaved and transmitted separately, reducing the overall system complexity while maintaining decoding performance.
Solution Approach 2:
The interleaver acts as an intermediary component between the LDPC encoder and the modulation stage. It receives the LDPC codeword, performs bit-group-wise interleaving to disperse adjacent bits, and outputs the interleaved sequence to the modulator. This intermediary function protects the LDPC decoding process from burst errors while adding structured complexity that can be efficiently implemented.
2Productivity
If bit group interleaving is applied to enhance receiving performance, then data transmission efficiency is improved, but the processing time increases due to additional interleaving operations
Solution Approach 1:
The bit group interleaving process divides the LDPC codeword into multiple bit groups of size M, where M is a common divisor of Nldpc and Kldpc. Each bit group is independently interleaved according to a predetermined pattern, which allows parallel processing of multiple groups simultaneously, reducing the overall processing time while improving transmission efficiency through better error dispersal.
Solution Approach 2:
The interleaving operation changes the positional parameters of bits within each bit group according to a predetermined permutation pattern. This parameter transformation disperses adjacent bits that may be affected by burst errors, improving the effectiveness of LDPC decoding without requiring complex real-time calculations, thus maintaining efficient processing speed.
3Reliability
If multiple interleaving stages (parity interleaver, group interleaver, block interleaver) are used to improve reception quality, then decoding performance is enhanced, but device complexity increases
Solution Approach 1:
The interleaving process is segmented into three distinct stages: parity interleaver (rearranging parity bits), group interleaver (rearranging bit groups), and block interleaver (rearranging blocks of bit groups). Each stage targets a specific aspect of error protection, and the segmented structure allows for modular implementation where each component can be optimized independently, reducing overall device complexity while achieving comprehensive reception quality improvement.
Solution Approach 2:
The three interleaving stages are combined in a cascaded configuration where the output of one stage feeds into the next. The parity interleaver processes parity bits first, then the group interleaver processes the resulting bit groups, and finally the block interleaver processes the complete blocks. This merging of multiple simple operations achieves complex error protection functionality more efficiently than a single complex interleaver would require.
Data Source
AI summary
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.