LDPC Bit Group Interleaver for 256-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation unless burst errors in digital broadcast channels are effectively distributed, requiring optimization of bit interleavers for specific modulation orders and error correction code lengths.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and a code rate of 10/15, using 256-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis with a parallel factor of 360, employing a specific permutation order for efficient error correction in next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bit-by-bit interleaver is used in BICM systems, then the system can provide high-level flexibility and bandwidth-efficient transmission, but performance degrades rapidly unless burst errors are appropriately distributed
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (45 groups of 360 bits each) and applies permutation-based interleaving to distribute burst errors across different bit groups. This segmentation approach maintains the flexibility of BICM while effectively combating burst errors by ensuring that errors concentrated in one time period are spread across multiple codeword positions.
Solution Approach 2:
The patent optimizes the interleaver by changing key parameters: using a specific permutation order (28, 20, 18, 38, 39, 2, 3, 30, 19, 4, 14, 36, 7, 0, 25, 17, 10, 6, 33, 15, 8, 26, 42, 24, 11, 21, 23, 5, 40, 41, 29, 32, 37, 44, 43, 31, 35, 34, 22, 1, 16, 27, 9, 13, 12), setting bit group size to 360 bits (parallel factor), and configuring 45 bit groups to match the LDPC codeword length of 16200 and code rate of 10/15.
2Reliability
If the bit interleaver is optimized for specific modulation orders and code rates, then error correction performance is improved, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-defining the optimal permutation order and bit group configuration based on the specific LDPC code parameters (length 16200, rate 10/15) and modulation scheme (256-QAM). This pre-optimization allows the system to achieve excellent error correction performance without requiring complex real-time adaptation, as the interleaver structure is predetermined and fixed.
3Reliability
If burst errors are distributed through bit group-based interleaving, then performance degradation is prevented, but the processing time increases
Solution Approach 1:
The patent segments the interleaving operation into 45 independent bit group permutations, where each group of 360 bits is permuted according to the predefined sequence. This segmentation allows for efficient parallel processing and reduces the overall processing time compared to bit-by-bit interleaving, while still achieving effective burst error distribution across the entire codeword.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.