LDPC Bit Group Interleaving for QPSK Burst Error Scattering

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 4/15, using a specific permutation order for bit group-based interleaving, optimized for QPSK modulation, to effectively distribute burst errors in next-generation broadcasting systems like ATSC 3.0.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in selecting modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels

Engineering Contradiction:
Improvebandwidth efficiencyVSAvoidperformance degradation due to burst errors
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the bit stream into blocks and applies interleaving at the block level rather than bit-by-bit. The LDPC codeword is divided into multiple blocks, and each block is interleaved independently using a block interleaver, which prevents burst errors from affecting the entire codeword and confines them to localized segments that can be more effectively corrected

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from one-dimensional bit-by-bit interleaving to two-dimensional block-based interleaving. By organizing bits into blocks with specific dimensions and applying interleaving patterns across these blocks, the system adds a spatial dimension to error distribution, effectively scattering burst errors across multiple blocks rather than concentrating them

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If a simple bit-by-bit interleaver structure is used, then the system complexity is reduced, but the system cannot effectively distribute burst errors occurring in the channel

Engineering Contradiction:
Improveinterleaver structure complexityVSAvoidburst error distribution capability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the codeword into multiple blocks and applies systematic interleaving patterns within each block. This segmentation allows the use of relatively simple intra-block interleaving schemes while achieving effective burst error distribution across the entire codeword through the combination of block division and patterned interleaving

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies interleaving only within each block rather than across the entire codeword in a complex manner. This partial action approach simplifies the interleaver design while still achieving effective error distribution, as the block-level interleaving is sufficient to scatter burst errors without requiring full-codeword complex interleaving

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If the bit interleaver is optimized for specific LDPC coder and modulation parameters, then the system achieves excellent performance for those parameters, but the system loses flexibility in adapting to different modulation orders and code rates

Engineering Contradiction:
Improveperformance for specific parametersVSAvoidflexibility in selecting modulation order and code parameters
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent designs a block interleaver structure that can accommodate different LDPC code lengths and modulation schemes by adjusting block size and interleaving pattern parameters. The same basic interleaver architecture serves multiple functions across different operating conditions, achieving optimized performance for specific parameters while maintaining adaptability through configurable parameters rather than fixed structure

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10826537B2Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and quadrature phase shift keying, and bit interleaving method using same
Publication Date: 2020.11.03 ELECTRONICS & TELECOMM RES INST
  • US10826537B2 patent drawing
  • US10826537B2 patent drawing
  • US10826537B2 patent drawing

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.