LDPC Bit Interleaver for 1024-Symbol Mapping and Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 2/15, using 1024-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, and integrated into a BICM device for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (each containing 360 bits) and applies separate interleaving operations to each group using different permutation patterns. This segmentation allows the system to handle burst errors more effectively by distributing them across different bit groups, thereby improving reliability without requiring a completely complex interleaver structure
Solution Approach 2:
The patent changes the interleaving parameters (permutation patterns, bit group sizes) to be specifically optimized for 1024-QAM modulation and LDPC codes with length 64800 and code rate 2/15. By adjusting these parameters to match the specific system configuration, the interleaver achieves better performance without unnecessary complexity
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but the adaptability to different configurations decreases
Solution Approach 1:
The patent defines specific interleaving parameters (bit group size of 360, number of groups of 180, specific permutation patterns) that are optimized for 1024-QAM and LDPC(64800, 2/15). These parameter changes provide excellent performance for the target configuration while maintaining a relatively simple structure that could be adapted to other configurations by modifying the parameters
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.