LDPC Bit Interleaver Layout for 16-Symbol Burst Error Spreading

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver is designed for an LDPC coder with a length of 16200 and code rate of 3/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order for effective distribution of burst errors, and a modulator performing 16-symbol mapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation

Engineering Contradiction:

ImproveperformanceVSAvoidinterleaver design

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The bit interleaver divides the codeword into multiple bit groups and applies different permutation patterns to different segments. This segmentation allows the system to handle burst errors more effectively by distributing them across different segments, thereby improving reliability without requiring a completely complex new structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs multiple permutation patterns that can be selected based on different channel conditions and error types. By changing the permutation parameter according to the situation, the system optimizes performance for specific burst error patterns while maintaining a relatively simple base structure

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but the adaptability to different configurations decreases

Engineering Contradiction:

Improveerror correction performanceVSAvoidflexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The bit interleaver is designed with a universal structure that can accommodate different modulation orders (QPSK, 16-QAM, etc.) and LDPC code parameters (code rates, block lengths). The same interleaver framework works across multiple configurations by adjusting permutation patterns, thus achieving both optimized performance and broad adaptability

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If burst errors are not distributed, then the system structure remains simple, but error correction capability deteriorates rapidly

Engineering Contradiction:

Improveerror correction capabilityVSAvoidinterleaving structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The bit interleaver performs preliminary distribution of bits into different groups and applies permutation patterns before transmission. This preliminary action ensures that burst errors occurring during transmission are already dispersed across different code positions, enabling the error correction decoder to handle them more effectively without requiring complex real-time processing

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10623022B2Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 16-symbol mapping, and bit interleaving method using same

Publication Date: 2020.04.14 ELECTRONICS & TELECOMM RES INST

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.