LDPC Bit Interleaving for 4096-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 5/15, using a processor to generate interleaved codewords on a bit group basis, with a specific permutation order for effective distribution of burst errors, and outputting the interleaved codewords for 4096-symbol mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in digital broadcast channels cause rapid performance degradation
Solution Approach 1:
The patent divides the codeword into multiple bit groups and applies separate permutation patterns to different segments. The interleaver processes the codeword by dividing it into N groups and applying different permutation functions P1, P2, ..., PN to each group, thereby distributing burst errors across different segments rather than concentrating them in one location.
Solution Approach 2:
The patent applies different permutation patterns to different bit groups within the codeword. Each bit group Xj is permuted using a specific pattern Pj that is tailored to its position and characteristics. This local customization of permutation patterns optimizes error distribution for each segment while maintaining overall system performance.
2Reliability
If the bit interleaver is optimized for specific LDPC coder parameters and modulation order, then performance improves, but the adaptability to different configurations decreases
Solution Approach 1:
The patent employs multiple configurable parameters including the number of bit groups N, different permutation patterns P1 through PN, and group sizes that can be adjusted based on the specific LDPC code rate and modulation scheme being used. This allows the interleaver to be optimized for specific configurations while maintaining the ability to adapt to different standards and requirements.
3Reliability
If burst errors are distributed through bit group-based interleaving, then performance degradation is prevented, but the computational complexity of the interleaving process increases
Solution Approach 1:
By dividing the codeword into N manageable bit groups and applying permutation operations independently to each group, the patent reduces the computational burden compared to processing the entire codeword as a single unit. Each permutation operation Pj operates on a smaller subset of bits, making the overall process more computationally efficient while still achieving effective error distribution.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.