LDPC Bit Group Interleaving for 4096-Symbol Burst Error Spreading
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation unless burst errors in digital broadcast channels are effectively distributed, necessitating an optimized bit interleaver design tailored to the modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and a code rate of 4/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order, and outputting it to a modulator for 4096-symbol mapping, optimized for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit interleaver is designed for optimized performance with specific modulation order and code rate, then error correction performance is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by optimizing the interleaver design for specific modulation orders (16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM) and code rates (4/15, 8/15, 12/15, 16/15). The interleaver structure and permutation patterns are tailored to match specific system parameters, achieving optimal error correction performance for each configuration while maintaining a systematic design approach that manages complexity through parameterization rather than ad-hoc design
Solution Approach 2:
The patent segments the 64800-bit LDPC codeword into multiple bit groups (e.g., 180 groups of 360 bits each) and applies separate interleaving operations to each group using different permutation patterns. This segmentation allows the complex interleaving operation to be broken down into manageable, repeatable units, improving both performance optimization and implementation efficiency
2Reliability
If burst errors are distributed through bit interleaving, then transmission reliability is improved, but processing time increases
Solution Approach 1:
The codeword is divided into multiple bit groups that can be interleaved independently and in parallel. This segmentation enables the distribution of burst errors across different groups while allowing simultaneous processing of multiple groups, thereby reducing overall processing time compared to sequential interleaving of the entire codeword
Solution Approach 2:
The interleaving permutation patterns are predetermined and stored in lookup tables based on the specific modulation order and code rate configuration. This preliminary preparation allows the interleaving operation to be executed efficiently during transmission without real-time computation, reducing processing time while maintaining optimal error distribution
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.