LDPC Bit Interleaver Layout for Burst-Error-Resistant 256 Mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 2/15, using 256-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, suitable for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (e.g., 180 bit groups of 360 bits each) and applies independent interleaving operations to each group using different permutation patterns. This segmentation allows the system to disperse burst errors across multiple bit groups, preventing any single error burst from affecting a large continuous portion of the codeword, thereby maintaining system performance under burst error conditions.
Solution Approach 2:
The patent introduces a bit group dimension in addition to the traditional bit-level interleaving. By organizing bits into groups and applying interleaving operations across both the bit group dimension and the bit dimension within each group, the system creates a two-dimensional interleaving structure that more effectively distributes burst errors in the channel.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance is maintained, but the device complexity increases
Solution Approach 1:
The patent optimizes the interleaver by changing key parameters including the bit group size (set to 360 bits), the number of bit groups (180 groups), and the specific permutation patterns used for each bit group. These parameter changes are specifically tailored to match the LDPC code parameters (64800-length, 2/15 code rate) and modulation scheme (256-QAM), achieving performance optimization for this specific configuration.
Solution Approach 2:
The patent applies different permutation patterns to different bit groups, allowing each bit group to be interleaved according to its specific position and characteristics. This local optimization approach enables the interleaver to be tailored to the specific requirements of each bit group while maintaining overall system performance, rather than applying a uniform interleaving pattern throughout.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.