LDPC Bit Interleaver Layout for Burst-Error-Tolerant 256-QAM
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 3/15, using 256-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, and integrated into a BICM device for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (180 groups of 360 bits each) and applies permutation to each group independently. This segmentation allows the interleaver to effectively distribute burst errors across different groups while maintaining a manageable structure that doesn't overly complicate the system design.
Solution Approach 2:
The patent optimizes specific parameters including the permutation order sequence, bit group size (360 bits), and number of groups (180 groups) to achieve optimal performance for 256-QAM modulation with LDPC code rate 3/15. These parameter changes are tailored to resolve the contradiction between reliability and complexity for specific system configurations.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance is improved, but the adaptability to different configurations is reduced
Solution Approach 1:
The patent establishes optimized parameter sets for specific configurations (256-QAM, LDPC 64800 length, code rate 3/15) while maintaining a modular structure that could potentially be adapted to other configurations by changing the permutation sequence and group parameters, thus balancing performance optimization with some degree of adaptability.
3Reliability
If burst errors are not distributed, then the system is simpler to implement, but error correction capability deteriorates rapidly
Solution Approach 1:
By segmenting the codeword into 180 bit groups and applying permutation across groups, the system achieves effective burst error distribution without requiring a completely complex interleaving structure. Each group can be processed independently, managing the complexity while improving reliability.
Solution Approach 2:
The interleaving operation is performed in advance before modulation, pre-distributing potential burst errors across different bit groups. This preliminary action ensures that even if burst errors occur during transmission, they will be spread out and more manageable for the decoder, improving error correction capability without adding complexity during the decoding phase.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.