LDPC Bit Group Interleaver for 64-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels unless the bit-by-bit interleaver is optimized for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and a code rate of 3/15, using 64-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, and integrated into a BICM device for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit-by-bit interleaver is used in BICM systems, then the system structure remains simple, but performance degrades rapidly due to burst errors in digital broadcast channels
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (e.g., 45 groups of 360 bits each) and applies permutation-based interleaving at the bit group level rather than individual bit level. This segmentation approach effectively distributes burst errors across different bit groups, preventing concentrated error patterns from overwhelming the error correction capability while maintaining system reliability.
Solution Approach 2:
The patent optimizes the interleaver by changing the permutation order parameter specifically tailored for 64-symbol mapping and LDPC code rate 3/15. By adjusting the permutation sequence parameters to match the specific modulation and coding parameters, the system achieves optimal performance without requiring complex structural modifications.
2Reliability
If the bit-by-bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but device complexity increases
Solution Approach 1:
The patent achieves optimization for specific modulation order (64-QAM) and code parameters (LDPC rate 3/15, length 16200) by modifying only the permutation order parameters rather than the fundamental interleaver structure. This allows the same interleaver architecture to be adapted to different parameters simply by changing the permutation sequence, avoiding complex redesign while maintaining optimized performance.
Solution Approach 2:
The patent designs a universal bit group-based interleaver structure that can handle multiple LDPC code rates and modulation schemes by simply adjusting the permutation order parameters. The same interleaver framework serves multiple functions across different broadcasting standards and parameters, reducing overall system complexity while maintaining optimized performance for each specific configuration.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.