LDPC Bit Interleaver Layout for Burst-Error-Resistant 16-Symbol Mapping
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 16200 and code rate of 4/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order for effective distribution of burst errors, and outputting the interleaved codeword for 16-symbol mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the codeword into multiple bit groups and applies different interleaving patterns to different segments. This segmentation allows burst errors to be distributed across multiple code blocks rather than concentrated in one location, thereby improving error correction performance while maintaining system reliability
Solution Approach 2:
The patent employs multiple interleaving patterns with different parameters (such as different permutation sequences and interleaving depths) that can be selected based on channel conditions and modulation orders. By changing interleaving parameters dynamically, the system optimizes performance under different operating conditions while effectively combating burst errors
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error correction performance improves, but device complexity increases
Solution Approach 1:
The patent uses a parameterized interleaver design where the interleaving pattern is determined by mathematical formulas involving the code length, modulation order, and other system parameters. This allows the interleaver to be optimized for specific configurations without requiring completely different designs, thereby managing complexity while maintaining high error correction performance
Solution Approach 2:
Different portions of the codeword are subjected to different interleaving treatments based on their specific requirements. For example, systematic bits and parity bits may use different interleaving patterns, and different modulation symbols may require different interleaving depths. This localized optimization improves overall performance without uniformly increasing complexity across the entire system
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.