LDPC Bit Interleaver Layout for Burst-Error-Resilient 64-Symbol Mapping
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 16200 and code rate of 3/15, using a processor to generate an interleaved codeword on a bit group basis, with a 64-symbol mapping modulator, and a specific permutation order to effectively distribute burst errors, optimized for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels
Solution Approach 1:
The patent applies segmentation by dividing the codeword into multiple bit groups (e.g., 360 bits per group for LDPC code length 16200) and performing interleaving at the bit group level rather than individual bit level. This segmentation allows the system to maintain bandwidth efficiency while effectively distributing burst errors across different bit groups, preventing concentrated error patterns that would cause performance degradation.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then the system can achieve excellent performance, but the device complexity increases due to the need for optimized designs
Solution Approach 1:
The patent applies parameter changes by providing specific optimization for LDPC codes with length 16200 and code rate 3/15, using bit group size of 360 bits (parallel factor), and employing a specific permutation order for bit group interleaving. These parameter optimizations enable excellent performance for next-generation broadcasting systems while maintaining manageable device complexity through standardized parameter sets.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.