LDPC Bit Interleaver Layout for QPSK Burst Error Distribution

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 2/15, using a specific permutation order for bit group-based interleaving, optimized for QPSK modulation, to effectively distribute burst errors in broadcasting systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation

Engineering Contradiction:

Improvesystem performanceVSAvoidinterleaver design complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The bit interleaver divides the LDPC codeword into multiple bit groups of equal size, where each bit group contains a specific number of bits. This segmentation allows the interleaver to process and distribute burst errors across different bit groups, preventing concentrated error patterns from overwhelming the decoding process and thereby improving system reliability without excessive complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The interleaver employs a dynamic permutation sequence that varies based on the bit group index and codeword position. This dynamic approach ensures that burst errors are distributed in a pseudo-random manner across the transmitted signal, maintaining good performance under various channel conditions while keeping the interleaver structure manageable through systematic permutation rules

Inventive Principle:

Principle #15Dynamics

2Reliability

If the bit interleaver is optimized for specific modulation order and code parameters, then performance is improved, but the adaptability to different configurations decreases

Engineering Contradiction:

Improveerror correction performanceVSAvoidflexibility to modulation and code parameters

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The interleaver design incorporates parameters such as bit group size, number of bit groups, and permutation sequences that can be adjusted according to the specific modulation order and LDPC code parameters being used. By changing these parameters, the same interleaver structure can be optimized for different configurations (e.g., different code rates, block lengths, or modulation schemes) while maintaining high performance, thus balancing specialization with adaptability

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10979079B2Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same

Publication Date: 2021.04.13 ELECTRONICS & TELECOMM RES INST

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.