LDPC Bit Interleaving Layout for Burst-Error-Resistant 64QAM
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Solution Overview
Problem
Current data transmission using LDPC codes faces challenges in maintaining favorable communication quality, particularly due to burst errors and erasures in communication paths, which degrade decoding performance and increase power consumption.
Innovation Solution
The implementation of a transmission method that includes parity interleaving and group-wise interleaving of LDPC codes, which separates parity bits to prevent simultaneous errors at check nodes, thereby enhancing resistance to burst errors and maintaining performance in AWGN channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are not interleaved, then device complexity is reduced, but reliability deteriorates due to burst errors affecting multiple check nodes simultaneously
Solution Approach 1:
The parity bits are segmented and distributed to different check nodes through interleaving. Specifically, the parity bits are divided into multiple groups and assigned to different check nodes, so that a burst error affecting one group does not simultaneously impact multiple check nodes, thereby improving reliability while maintaining manageable complexity through systematic segmentation
Solution Approach 2:
The patent introduces a new dimension of organization by mapping parity bits to check nodes in a two-dimensional structure (parity bit index vs. check node index). This dimensional transformation allows burst errors to be spread across different dimensions, preventing simultaneous failure of multiple check nodes while keeping the interleaving logic structured and implementable
2Reliability
If interleaving is applied to separate parity bits, then reliability improves against burst errors, but device complexity increases due to additional interleaving operations
Solution Approach 1:
The interleaver segments the parity bits into multiple subsets, each assigned to different check nodes. This segmentation is achieved through a systematic mapping process that divides the parity bit sequence into groups, ensuring that burst errors are distributed across different segments rather than concentrated on a single check node, thus improving reliability while maintaining structured complexity
Solution Approach 2:
The interleaving operation is performed preliminarily during the encoding stage, distributing parity bits to different check nodes before transmission. This preliminary action ensures that when burst errors occur during transmission, their impact is already mitigated by the pre-established distribution pattern, improving decoding performance without requiring complex real-time processing at the receiver
Data Source
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AI summary
The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.