LDPC Bit Interleaving for 8PSK and 16APSK Error Floor Reduction

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Solution Overview

Problem

In data transmission systems using LDPC codes, such as DVB-S.2, DVB-T.2, and DVB-C.2, ensuring good communication quality is challenging due to error floor phenomena and burst errors, which deteriorate decoding performance and increase power consumption.

Innovation Solution

A data processing device and method that interleave LDPC code bits to allocate strong code bits to weak symbol bits, using a demultiplexer to perform interchange processing and interleaving techniques like parity interleave and column twist interleave, to enhance error tolerance and decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC code bits are directly mapped to modulation symbols without interleaving, then the mapping process is simple, but error floor phenomena and burst errors deteriorate decoding performance

Engineering Contradiction:
Improvedecoding performanceVSAvoidinterleaving complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC code bits are segmented into multiple groups based on their reliability characteristics (strong code bits and weak code bits). This segmentation allows different groups to be mapped to different modulation symbol positions, optimizing overall system performance by ensuring that more reliable code bits are placed in less robust symbol positions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the LDPC code bit sequence are assigned different qualities or priorities. Specifically, weak code bits (which are more susceptible to errors) are identified and separately handled from strong code bits. This local quality differentiation enables targeted protection strategies where weak code bits are mapped to more robust symbol positions.

Inventive Principle:
Principle #3Local quality

2Reliability

If strong code bits are allocated to weak symbol bits through interleaving, then error tolerance is enhanced, but the processing complexity increases

Engineering Contradiction:
Improveerror toleranceVSAvoidinterchange processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The identification and separation of strong and weak code bits is performed in advance before the actual mapping process. This preliminary classification allows the subsequent mapping to proceed in a more systematic and efficient manner, reducing the complexity of real-time processing while maintaining optimal error tolerance characteristics.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If conventional mapping methods are used, then implementation is straightforward, but communication quality deteriorates due to burst errors

Engineering Contradiction:
Improvecommunication qualityVSAvoidimplementation ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The mapping strategy dynamically adjusts based on the identified characteristics of code bits (strong vs. weak). By changing the mapping parameters adaptively - specifically which code bit goes to which symbol position based on their relative strengths - the system optimizes communication quality while managing implementation complexity through systematic rules.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2993792B1LDPC coded modulation in combination with 8PSK and 16apsk
Publication Date: 2022.06.22 SATURN LICENSING LLC
  • EP2993792B1 patent drawingFigure 1
  • EP2993792B1 patent drawingFigure 2
  • EP2993792B1 patent drawingFigure 3

AI summary

In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.