LDPC Bit Interleaving for 16-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 3/15, using 16-symbol mapping, which interleaves the LDPC codeword on a bit group basis according to a specific permutation order, effectively distributing burst errors and enhancing error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but performance degrades rapidly due to burst errors in digital broadcast channels
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (e.g., 180 bit groups of 360 bits each) and applies independent interleaving operations to each group using different permutation orders. This segmentation allows the system to distribute burst errors across multiple groups while maintaining manageable complexity for each individual interleaving operation, thereby improving error correction performance without excessive device complexity
Solution Approach 2:
The patent applies different permutation orders to different bit groups based on their specific positions and characteristics. Each bit group receives a tailored interleaving pattern optimized for its local requirements, allowing the system to address burst errors more effectively in different regions of the codeword while maintaining overall system performance
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance is maintained, but the system loses flexibility in adapting to different broadcasting standards
Solution Approach 1:
The patent employs dynamic permutation orders that can be adjusted based on modulation order, code rate, and codeword length. The interleaving pattern is not fixed but can be adapted to match different broadcasting standards and channel conditions, allowing the system to maintain optimized performance across various configurations including ATSC 3.0, DVB-T2, and other next-generation broadcasting systems
Solution Approach 2:
The patent changes key parameters of the interleaver including permutation order, bit group size, and number of groups based on the specific broadcasting standard and channel conditions. By making these parameters adjustable rather than fixed, the system can optimize performance for each specific application while maintaining a unified interleaver structure
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.