LDPC Bit Interleaving Layout for Burst-Error-Resistant Decoding

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Solution Overview

Problem

Existing data transmission methods using LDPC codes face challenges in maintaining favorable communication quality, particularly due to burst errors and erasures, which degrade decoding performance and increase power consumption.

Innovation Solution

The implementation of parity interleaving and group-wise interleaving in conjunction with block interleaving enhances the error rate of LDPC codes, separating parity bits to prevent simultaneous errors at check nodes, thereby improving resistance to burst errors and maintaining decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If block interleaving is used alone, then the transmission structure is simple, but burst errors cause simultaneous errors at check nodes degrading decoding performance

Engineering Contradiction:
Improvedecoding performanceVSAvoidinterleaving structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the interleaving process into three independent stages: parity interleaving (separating parity bits), group-wise interleaving (rearranging bit groups), and block interleaving (final arrangement). This segmentation allows each stage to address specific error patterns without requiring a single complex interleaver, thereby improving decoding performance while keeping individual stages manageable in complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines three different interleaving methods (parity interleaving, group-wise interleaving, and block interleaving) into a unified transmission structure. By merging these techniques, the system achieves superior error correction performance against burst errors compared to using any single interleaving method alone, while distributing the computational complexity across multiple simpler stages.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If parity bits are transmitted contiguously, then the transmission process is simple, but burst errors cause simultaneous errors at check nodes

Engineering Contradiction:
Improveerror resistanceVSAvoidbit arrangement complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parity interleaving as the first stage, which segments and disperses parity bits throughout the code bit sequence rather than transmitting them contiguously. This segmentation prevents burst errors from affecting multiple parity bits simultaneously, thereby improving error resistance while adding only a single-stage transformation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs parity interleaving before group-wise and block interleaving operations. This preliminary action of dispersing parity bits early in the transmission process ensures that subsequent interleaving stages operate on already-protected data, preventing simultaneous errors at check nodes before they can occur.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If no interleaving is applied, then the processing speed is fast, but communication quality deteriorates due to burst errors

Engineering Contradiction:
Improvecommunication qualityVSAvoidinterleaving processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the interleaving operation into three distinct, independently implementable stages. This segmentation allows each stage to be processed efficiently with simple transformation rules, maintaining processing speed while collectively achieving superior communication quality through the combined effect of all three stages against burst errors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges three complementary interleaving techniques into a unified processing pipeline. Each technique addresses different aspects of error protection, and their combination provides robust communication quality improvement without requiring any single complex processing operation, thus balancing quality enhancement with processing efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3675368B1Transmission and reception of an LDPC code of length 69120 and code rate of 7/16 with bit interleaving adapted to QPSK, 16QAM, 64QAM and 256qam
Publication Date: 2024.01.10 SONY GROUP CORP
  • EP3675368B1 patent drawingFigure 1~2
  • EP3675368B1 patent drawingFigure 3
  • EP3675368B1 patent drawingFigure 4

AI summary

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups 0 to 191. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.