LDPC Bit Interleaving for High-Order Modulation Mapping
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Solution Overview
Problem
In communication and broadcasting systems, high digital communication systems face challenges due to noise, fading, and inter-symbol interference, which affect data throughput and reliability, particularly in next-generation mobile communication and digital broadcasting. The performance of Low Density Parity Check (LDPC) codes is hindered by the complexity of mapping codeword bits onto high-order modulation bits.
Innovation Solution
A transmitting apparatus and method that includes an encoder for generating LDPC codewords, an interleaver to reorder these codewords, and a modulator to map them onto modulation symbols. The interleaver divides columns into two parts, ensuring that bits from the same bit group are written in the same column in the first part and divided across multiple columns in the second part, optimizing the mapping process for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If LDPC codeword bits are mapped onto high order modulation bits, then data throughput is improved, but mapping complexity increases
Solution Approach 1:
The interleaver divides the LDPC codeword into multiple bit groups, where each bit group contains a specific number of bits. This segmentation allows the mapping process to be broken down into manageable units, reducing the overall mapping complexity while maintaining high data throughput through efficient parallel processing of bit groups.
Solution Approach 2:
The patent introduces a two-dimensional interleaving structure with rows and columns, where bits are arranged in a matrix format. This dimensional transformation converts the complex one-to-one mapping problem into a structured two-dimensional arrangement, simplifying the mapping process while enabling efficient high-order modulation through the row-column interleaving mechanism.
2Reliability
If iterative decoding based on sum-product algorithm is applied, then decoding performance approaches channel capacity, but decoding complexity increases
Solution Approach 1:
The LDPC code is defined by a sparse parity check matrix with structured zero patterns, which segments the decoding computations into independent or lightly coupled blocks. This segmentation enables the sum-product algorithm to process fewer non-zero elements, reducing decoding complexity while maintaining near-capacity performance through efficient message passing across the segmented structure.
3Reliability
If noise and inter-symbol interference are mitigated, then communication reliability is improved, but system complexity increases
Solution Approach 1:
The interleaver is positioned before the modulator in the transmission chain, performing preliminary reordering of the LDPC codeword bits before modulation. This preliminary action distributes the impact of noise and inter-symbol interference across different coded bits, enabling the subsequent decoding process to more effectively mitigate these effects and improve communication reliability.
Data Source
AI summary
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns including a plurality of rows, respectively, and comprises: a block interleaver configured to divide each of the plurality of columns into a first part and a second part, and interleave a plurality of bit groups constituting the LDPC codeword, all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.


