LDPC Bit Interleaving for Reliable High-Order Modulation
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Solution Overview
Problem
Conventional LDPC coded transmission schemes face challenges in achieving low error rates, especially with high-order modulation, due to the non-systematic nature of NR LDPC codes and the lack of efficient bit-level interleaving strategies, which affect reliability and coding gain.
Innovation Solution
The proposed solution involves a transmitting device that rearranges the rows of the matrix by circularly shifting systematic and parity-check bits to different modulation label positions based on reliability, and a receiving device that decodes de-rate-matched soft codewords, informed by control messages, to improve error protection and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional NR LDPC codes with high-order modulation are used, then spectral efficiency is improved, but error rate increases due to non-systematic nature and lack of bit-level interleaving
Solution Approach 1:
The patent segments the codeword into systematic bits and parity-check bits, and further segments the modulation labels into different reliability groups. This segmentation allows selective mapping of systematic bits to high-reliability modulation labels and parity bits to lower-reliability labels, resolving the contradiction between high spectral efficiency and low error rate in conventional non-systematic LDPC codes
Solution Approach 2:
The patent applies local quality by assigning different mapping strategies to different bit types within the codeword. Systematic bits are mapped to modulation labels with higher reliability (e.g., more robust constellation positions), while parity-check bits are mapped to labels with lower reliability. This localized differentiation improves overall reliability without sacrificing spectral efficiency
2Reliability
If systematic bits are mapped to high-reliability modulation labels, then error protection is improved, but device complexity increases due to additional interleaving operations
Solution Approach 1:
The patent performs preliminary action by pre-arranging systematic and parity-check bits in specific positions before modulation mapping. The bit-level interleaver is designed to place systematic bits in positions that will map to high-reliability modulation labels, eliminating the need for complex real-time rearrangement operations and reducing device complexity while maintaining improved error protection
Data Source
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AI summary
The invention relates to a transmitting device (100) for a communication system (500). The transmitting device (100) obtains an information message comprising information bits addressed for a receiving device (300) and encode the information message so as to obtain a codeword. The transmitting device (100) further rate-matches the codeword so as to produce a rate-matched codeword comprising systematic bits and parity-check bits. Furthermore, the transmitting device (100) jointly interleave the systematic bits and parity-check bits of the rate- matched codeword so as to obtain an interleaved codeword, wherein the systematic bits of the interleaved codeword are mapped to modulation label positions of a modulation constellation with first reliabilities and the parity-check bits of the interleaved codeword are mapped to modulation label positions of the modulation constellation with second reliabilities. Furthermore, the invention also relates to a corresponding receiving device (300), corresponding methods and a computer program.