LDPC Bit Interleaving Layout for Burst-Error-Resistant QPSK

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Solution Overview

Problem

Existing data transmission methods using LDPC codes face challenges in maintaining favorable communication quality due to burst errors and erasures, particularly in AWGN channels and multipath environments, which degrade decoding performance and increase power consumption.

Innovation Solution

The implementation of a transmission method that includes parity interleaving and group-wise interleaving of LDPC codes, along with a specific configuration of the parity check matrix, to enhance resistance to burst errors and maintain performance in AWGN channels, involving the use of a parity check matrix with a step structure and cyclic or pseudo-cyclic structures to separate variable nodes connected to the same check node, thereby preventing simultaneous errors and improving decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC code transmission is used without specific interleaving, then the system is simple to implement, but burst errors and erasures degrade decoding performance and communication quality

Engineering Contradiction:

Improvedecoding performanceVSAvoidinterleaving structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC code is divided into multiple blocks, and bit interleaving is applied within each block. This segmentation allows the code to be processed in manageable units while maintaining error correction capability, resolving the contradiction between reliability and complexity by breaking down the large-scale interleaving problem into smaller, more manageable block-level operations

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic interleaving patterns that adapt to different channel conditions and error types. The bit interleaving configuration can be adjusted based on the specific communication scenario, allowing the system to optimize between simplicity and performance depending on operational requirements

Inventive Principle:

Principle #15Dynamics

2Reliability

If strong error correction is implemented to resist burst errors, then communication quality improves, but power consumption increases

Engineering Contradiction:

Improvecommunication qualityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies bit interleving at the block level rather than across the entire code, implementing partial action that provides sufficient error protection for burst errors without the full computational overhead of complete code-level interleaving. This reduces power consumption while maintaining communication quality

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The interleaving block size and pattern are optimized parameters that balance error correction strength with computational complexity. By carefully selecting these parameters, the system achieves adequate protection against burst errors while controlling the power consumption of the decoding process

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentEP3579430B1Bit interleaving for LDPC codes of length 69120 and rate 2/16 in combination with qpsk

Publication Date: 2022.10.12 SONY GROUP CORP

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AI summary

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.