LDPC Bit Mapping for 8PSK and 16APSK Error Floor Reduction
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Solution Overview
Problem
In data transmission systems using LDPC codes, such as DVB-S.2, DVB-T.2, and DVB-C.2, ensuring good communication quality is challenging due to error floor phenomena and burst errors, which deteriorate decoding performance and increase power consumption.
Innovation Solution
A data processing device and method that employs a demultiplexer to interchange positions of LDPC code bits, allocating weak error bits to strong symbol bits, and uses parity and column twist interleaving to enhance tolerance against burst errors and erasures, thereby improving decoding performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC code mapping to orthogonal modulation symbols is used, then data transmission is performed, but error floor phenomena and burst errors occur which deteriorate decoding performance and increase power consumption
Solution Approach 1:
The LDPC code bits are segmented into different groups based on their error correction strength (strong error bits and weak error bits). The demultiplexer separates these groups and allocates them to different symbol bit positions, allowing differential protection strategies for different bit segments.
Solution Approach 2:
Different allocation strategies are applied to different types of LDPC code bits. Strong error bits are allocated to symbol bits that can tolerate errors, while weak error bits are allocated to more protected symbol bit positions. This local differentiation optimizes overall system reliability.
2Reliability
If LDPC code bits are directly mapped to modulation symbols, then transmission is performed, but burst errors and erasures deteriorate decoding performance
Solution Approach 1:
The interleaving structure is segmented into multiple stages: demultiplexing stage that separates strong and weak error bits, allocation stage that assigns bits to different symbol positions, and parity interleaving stage that provides additional protection. This segmentation makes the complex interleaving process more manageable and effective.
Solution Approach 2:
The demultiplexer performs preliminary sorting and allocation of LDPC code bits before modulation. By pre-arranging strong and weak error bits in optimal positions before transmission, the system prepares for potential burst errors and erasures, improving tolerance without adding complex real-time processing.
3Use of energy by moving object
If conventional mapping is used, then data transmission occurs, but power consumption increases due to error correction requirements
Solution Approach 1:
The system changes the allocation parameter of LDPC code bits to modulation symbols based on error bit strength. By optimizing which bits go to which symbol positions, the system achieves better error correction efficiency, reducing the need for repeated decoding attempts and thereby lowering power consumption.
Data Source
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AI summary
The present technology relates to a data processing device and data processing method that are capable of ensuring good communication quality in data transmission using an LDPC code. A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. When 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i + 1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i + 1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b0 is interchanged with a bit y1, a bit b1 is interchanged with a bit y0, and a bit b2 is interchanged with a bit y2. The present technology can be applied to a case of performing data transmission using an LDPC code, for example.