LDPC Bit Permutation for 256QAM Reception Reliability
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Solution Overview
Problem
The reception performance of receivers in bit-interleaved coding and modulation systems can be improved by optimizing the permutation rules applied to LDPC codeword bits before mapping, specifically for LDPC codes and constellations used by transmitters and receivers.
Innovation Solution
The proposed method optimizes permutation rules for LDPC codeword bits before mapping, utilizing a bit-to-cell demultiplexer that applies specific permutation rules based on the LDPC code rate and QAM constellation, enhancing the association between LDPC codeword bits and constellation symbols, thereby improving reception performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard bit-interleaving and demultiplexing is used, then system complexity is reduced, but reception performance deteriorates
Solution Approach 1:
The patent applies different permutation rules based on the specific LDPC code rate and QAM constellation configuration. By changing the permutation parameters according to the code rate (e.g., 1/2, 2/3, 3/4, 5/6) and modulation scheme (e.g., 16QAM, 64QAM, 256QAM), the system optimizes reception performance for each specific configuration without requiring a completely different system architecture.
2Reliability
If permutation rules are optimized for specific LDPC codes and constellations, then reception performance is improved, but system adaptability decreases
Solution Approach 1:
The patent implements a dynamic permutation rule selection mechanism that adapts to different LDPC code rates and QAM constellation configurations. The system dynamically chooses the appropriate permutation rule from a set of predefined rules based on the detected code rate and modulation scheme, allowing optimal performance across multiple configurations without requiring manual reconfiguration.
Data Source
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AI summary
Information bits are encoded (115) according to a low density parity check, LDPC, code with code rate 7/15 and a codeword length of 16200. The resulting codeword bits are bit-interleaved (120) by means of a parity interleaver (121) and a column-row interleaver (125). The interleaved bits are demultiplexed (130) into 8 sequences of bits, which are permuted according to a predetermined permutation rule: v0 = b2, v1 = b6, v2 = b0, v3 = b1, v4 = b4, v5 = b5, v6 = b3, v7 = b7 and mapped onto symbols of a 256QAM constellation (140).