Bit-Flipping LDPC Decoding with Out-of-Order Column Scheduling
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Solution Overview
Problem
Non-volatile memory devices, particularly SSDs using multi-level NAND flash, face challenges in data integrity due to inherent unreliability, requiring strong error-correction codes that increase storage space and latency, necessitating more efficient decoding approaches for improved convergence properties.
Innovation Solution
Processing circulant-columns in an irregular quasi-cyclic low-density parity-check (LDPC) code in an out-of-order manner based on flipping energies, utilizing a vertically shuffled scheduling (VSS) operation to enhance the convergence of bit-flipping decoders, which involves computing flipping energies, selecting columns based on metrics, and performing message passing algorithms between variable and check nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strong error-correction codes are used to improve data reliability, then data integrity is improved, but storage space increases and latency increases
Solution Approach 1:
The patent implements dynamic processing of circulant-columns based on flipping energies, where the processing order is adaptively determined by computing flipping energies for each column and processing them in descending order of energy. This dynamic approach allows the decoder to focus computational resources on the most error-prone columns first, improving convergence speed and reducing latency while maintaining data integrity through efficient error correction
Solution Approach 2:
The patent changes the processing parameter from sequential indexing to energy-based ordering. By computing flipping energies as a new parameter and using it to determine processing order, the system optimizes the decoding process to converge faster, thereby reducing the time penalty associated with using strong error-correction codes
2Reliability
If strong error-correction codes are used to improve data reliability, then data integrity is improved, but storage space increases
Solution Approach 1:
The patent applies partial processing by focusing computational effort on a subset of circulant-columns that have the highest flipping energies. Instead of uniformly processing all columns with equal resources, the system identifies and prioritizes the most critical columns for error correction, achieving effective error correction with optimized resource utilization and reduced storage overhead for parity bits
3Productivity
If sequential processing of circulant-columns is used, then device complexity is low, but convergence speed is slow
Solution Approach 1:
The patent performs preliminary computation of flipping energies for all circulant-columns before the actual decoding process. This preliminary action ranks the columns in advance based on their error-proneness, allowing the main decoding process to proceed in an optimized order. This upfront preparation enables faster convergence without significantly increasing the complexity of the core decoding algorithm
Solution Approach 2:
The system uses the inherent flipping energy characteristics of the data itself to determine processing order, rather than requiring external control or complex scheduling mechanisms. The flipping energies naturally guide the decoding process to handle the most problematic columns first, making the system self-optimizing without adding substantial control complexity
Data Source
AI summary
Devices, systems and methods for improving the convergence of a bit-flipping decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, computing a plurality of flipping energies for each column of a first subset of columns from the plurality of columns of circulant matrices, computing, based on the plurality of flipping energies, one or more metrics, selecting, based on the one or more metrics, a second subset of columns from the first subset of columns in an order that is different from a sequential indexing order of the second subset of columns, determining, based on processing the second subset of columns using a vertically shuffled scheduling operation, a candidate version of the transmitted codeword.