LDPC Bit-Group Interleaving for 1024-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 2/15, using 1024-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, suitable for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels
Solution Approach 1:
The patent divides the bit stream into bit groups of length L (where L is a parallel factor of the LDPC codeword length N). Each bit group is processed independently through the interleaving operation, allowing burst errors to be distributed across multiple bit groups rather than concentrated in one location. This segmentation approach maintains the flexibility of BICM while mitigating burst error effects.
Solution Approach 2:
The patent introduces a new dimension of interleaving at the bit group level, using a permutation operation π(j) that rearranges the order of bit groups. This transforms the one-dimensional bit sequence into a two-dimensional structure (bit groups arranged in permuted order), effectively distributing burst errors across different dimensions of the data structure.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then it can effectively distribute burst errors, but the device complexity increases due to the need for specific permutation orders and memory structures
Solution Approach 1:
The patent optimizes the interleaver by carefully selecting specific parameters: bit group length L as a parallel factor of N, and code rate r as a rational number p/q where q divides N/L. These parameter choices enable the use of simple permutation operations and memory structures while achieving effective burst error distribution. The specific permutation order π(j) is designed to work efficiently with these parameters.
Solution Approach 2:
The patent creates a universal bit interleaver structure that can handle multiple code rates and modulation schemes by using parameterized designs. The interleaver works with any LDPC codeword length N and parallel factor L, and any code rate r=p/q where q|(N/L). This multi-functionality reduces the need for separate optimized interleavers for each specific configuration.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.