LDPC Bit-Group Interleaving for Broadcast Decoding Reliability

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Solution Overview

Problem

Current broadcasting communication systems face challenges in providing high decoding and receiving performance for digital broadcasting services, particularly with the increasing demand for multi-channel, wideband, and high-quality digital services.

Innovation Solution

A transmitting apparatus and method that employs LDPC encoding, interleaving, and modulation to efficiently map and transmit bits, utilizing an encoder to generate LDPC codewords, an interleaver to rearrange bit groups, and a modulator to map these bits onto modulation symbols, specifically using a parity interleaver, group interleaver, and block interleaver to enhance decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC encoding is used to improve decoding performance, then error correction capability is enhanced, but system complexity increases

Engineering Contradiction:
Improvedecoding performanceVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC codeword is divided into multiple bit groups, and each bit group is further segmented into sub-bit groups for selective interleaving. This segmentation allows the system to apply complex processing only to specific portions of the data, maintaining high decoding performance while reducing overall system complexity by avoiding full-codeword processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different interleaving strategies are applied to different bit groups based on their position and importance. The method applies bit-group-wise interleaving to certain groups and sub-bit-group-wise interleaving to others, creating local variations in processing quality that optimize the balance between performance and complexity.

Inventive Principle:
Principle #3Local quality

2Reliability

If bit groups are rearranged through interleaving to improve receiving performance, then decoding reliability is enhanced, but processing time increases

Engineering Contradiction:
Improvereceiving performanceVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The interleaving process is segmented into bit-group-wise and sub-bit-group-wise operations, allowing parallel processing of different bit groups. This reduces the total processing time compared to sequential full-codeword interleaving while maintaining the performance benefits of rearrangement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of interleaving the entire LDPC codeword, the method applies partial interleaving only to selected bit groups and sub-bit groups. This partial action achieves sufficient performance improvement without the time cost of complete codeword processing.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If multiple interleaving stages are applied to enhance decoding performance, then error correction capability is improved, but device complexity increases

Engineering Contradiction:
Improvedecoding performanceVSAvoidinterleaver complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The complex multi-stage interleaving process is segmented into distinct bit-group-wise and sub-bit-group-wise stages, each handling specific portions of the codeword. This segmentation allows the use of simpler, modular interleaver designs for each stage rather than a single complex interleaver, reducing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different interleaving depths and methods are applied locally to different bit groups based on their requirements. Not all bit groups undergo the same level of interleaving, which reduces the total computational burden and device complexity while maintaining performance where it matters most.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9780808B2Transmitter apparatus and bit interleaving method thereof
Publication Date: 2017.10.03 SAMSUNG ELECTRONICS CO LTD
  • US9780808B2 patent drawing
  • US9780808B2 patent drawing
  • US9780808B2 patent drawing

AI summary

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.