LDPC Bit-Group Interleaving for Burst-Error-Resilient 256 Mapping
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 2/15, using a specific permutation order for bit group-based interleaving, optimized for 256-symbol mapping, to effectively distribute burst errors in next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but performance degrades rapidly due to burst errors in digital broadcast channels
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (e.g., 180 bit groups for a 64800-length codeword with parallel factor 360) and applies permutation-based interleaving to these groups. This segmentation approach distributes burst errors across different bit groups while maintaining a relatively simple interleaver structure based on predefined permutation sequences.
2Reliability
If the bit interleaver is optimized for specific modulation order and code rate parameters, then error correction performance improves, but the interleaver becomes less flexible for different broadcasting standards
Solution Approach 1:
The patent employs parameter-based permutation sequences where the interleaving pattern is determined by parameters such as the parallel factor and code rate. For example, with a parallel factor of 360 and code rate 2/15, specific permutation sequences are applied. This allows the same interleaver structure to be adapted to different modulation orders (e.g., 256-QAM) and code rates by simply changing the permutation parameters rather than redesigning the entire interleaver.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.