LDPC Bit Group Interleaving for Modulation Mapping Reliability
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Solution Overview
Problem
There is a need for improved decoding and receiving performance in digital broadcasting services, particularly in high quality digital televisions and portable multimedia devices, due to the increasing demand for efficient digital broadcasting methods.
Innovation Solution
A transmitting apparatus and method that utilizes an LDPC codeword encoder, interleaver, and modulator to map bits from a predetermined bit group onto a modulation symbol, employing a parity check matrix and cyclic shift parameters to optimize bit arrangement and interleaving, thereby enhancing decoding and receiving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC encoding with parity check matrix is used, then decoding performance is improved, but device complexity increases
Solution Approach 1:
The LDPC codeword is divided into multiple bit groups, and the interleaving process segments these bit groups for independent processing. This segmentation allows the encoder to handle large block sizes efficiently by breaking down the complex encoding task into manageable segments, thereby improving decoding performance without proportionally increasing device complexity
Solution Approach 2:
The patent introduces bit group-wise interleaving as an additional processing dimension beyond standard LDPC encoding. By adding this interleaving dimension that operates on bit groups rather than individual bits, the system achieves enhanced decoding performance through improved error distribution while maintaining manageable encoder complexity through structured group processing
2Reliability
If bit group interleaving is applied, then receiving performance is improved, but processing time increases
Solution Approach 1:
The interleaving process is segmented to operate on bit groups rather than individual bits, reducing the total number of operations required. By processing M bits as a group (where M is a common divisor of Nldpc and Kldpc), the system achieves improved receiving performance through better error distribution while minimizing processing time overhead compared to bit-by-bit interleaving
Solution Approach 2:
The patent optimizes the bit group size parameter M to balance receiving performance and processing time. By selecting M as a common divisor of Nldpc and Kldpc that satisfies Qldpc=(Nldpc-Kldpc)/M, the system achieves optimal interleaving effectiveness while maintaining efficient processing speed, thus improving receiving performance without excessive time loss
3Reliability
If multiple interleaving stages are used, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The interleaver is segmented into functional units that process bit groups independently, allowing multiple interleaving stages to be implemented with manageable complexity at each stage. This modular segmentation enables the system to achieve high data transmission reliability through multi-stage interleving while keeping individual stage complexity low through standardized group processing
Solution Approach 2:
The bit group interleaving mechanism serves multiple functions simultaneously: it distributes errors across bit groups, optimizes mapping onto modulation symbols, and prepares data for subsequent processing stages. This multi-functionality allows the interleaver to achieve enhanced transmission reliability through coordinated multi-stage processing without proportionally increasing device complexity
Data Source
AI summary
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.