LDPC Bit-Group Interleaver for 256-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation unless burst errors in digital broadcast channels are appropriately distributed, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 2/15, using 256-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, effectively distributing burst errors and improving error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit-by-bit interleaver is used in BICM systems, then the system can provide high-level flexibility and excellent performance, but rapid performance degradation occurs unless burst errors are appropriately distributed
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (45 groups of 360 bits each) and performs interleaving at the bit group level rather than individual bit level. This segmentation allows burst errors to be distributed across multiple bit groups, preventing concentrated error patterns that would degrade performance.
Solution Approach 2:
The patent introduces a new dimension of interleaving by organizing bits into a two-dimensional structure (45 bit groups × 360 bits per group) and applying permutation across the group dimension. This dimensional transformation enables more effective burst error distribution compared to traditional one-dimensional bit-by-bit interleaving.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then excellent performance is achieved, but the design becomes complex and specific to particular configurations
Solution Approach 1:
The patent optimizes specific parameters including bit group size (360 bits), number of bit groups (45), and permutation sequence to achieve excellent performance for LDPC codes with length 16200 and code rate 2/15. These parameter optimizations provide a balanced solution that achieves high performance without requiring complex adaptive mechanisms.
3Reliability
If burst errors are distributed through interleaving, then error correction performance improves, but the interleaving process requires additional processing time and complexity
Solution Approach 1:
The patent applies preliminary interleaving at the bit group level before modulation, organizing the LDPC codeword into 45 bit groups and applying permutation sequences in advance. This preliminary action ensures that when burst errors occur during transmission, they are already distributed across different bit groups, reducing the need for complex deinterleaving and reprocessing at the receiver.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.