LDPC-CC Encoding for Multiple Coding Rates With Low Complexity
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Solution Overview
Problem
Current LDPC-CC encoders and decoders face challenges in supporting multiple coding rates with low computational complexity while maintaining high received data quality, as existing methods either increase computational complexity or compromise on data quality.
Innovation Solution
The development of LDPC-CC encoding methods that utilize specific parity check polynomials and matrix configurations to achieve a regular LDPC code with column weights of 4 or 8, allowing for efficient belief propagation and improved error correction capabilities, thereby supporting multiple coding rates with reduced computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If puncturing processing or padding processing is executed on transmission information sequence to adjust length, then the transmission information sequence can be adjusted to match LDPC code block length, but the coding rate changes and redundant sequence transmission occurs
Solution Approach 1:
The patent changes the fundamental parameter of code structure from block code to convolutional code. LDPC-CC uses a convolutional encoding structure with shift registers and modulo-2 adders that processes information sequences continuously without requiring fixed-length blocks, thereby eliminating the need for padding or puncturing operations and maintaining the original coding rate.
Solution Approach 2:
The LDPC-CC encoder is designed with universal applicability to handle information sequences of any length. The convolutional structure with M+1 shift registers of bit-length c and modulo-2 adders provides a flexible framework that can encode variable-length sequences without modification, making the system adaptable to different transmission requirements without introducing redundancy.
2Adaptability or versatility
If multiple coding rates are supported using conventional LDPC-CC methods, then coding rate flexibility is improved, but computational complexity increases
Solution Approach 1:
The patent implements dynamic selectability of coding rates through a configuration parameter m (where m ≥ 2). The parity check matrix structure allows dynamic adjustment between different coding rates by selecting different values of m, enabling the system to adapt to varying channel conditions and transmission requirements without requiring multiple separate encoders or complex computational procedures.
Solution Approach 2:
The LDPC-CC encoder is segmented into M+1 shift registers of bit-length c with specific connection patterns to modulo-2 adders. This segmentation creates a modular structure where each register and adder combination can be selectively activated based on the desired coding rate, reducing the computational burden compared to conventional methods that require processing entire blocks at once.
3Device complexity
If LDPC-CC encoder uses simple circuitry with M+1 shift registers and modulo 2 adder, then device complexity is reduced, but supporting multiple coding rates with high received quality becomes difficult
Solution Approach 1:
The patent changes the parity check matrix parameters to achieve column weights of 4 or 8, which optimizes the balance between circuit simplicity and error correction performance. This parameter optimization allows the simple modular circuit structure to achieve high received quality by ensuring sufficient redundancy and error detection capability while maintaining low computational complexity.
Solution Approach 2:
The encoder combines multiple shift registers and modulo-2 adders in a composite modular structure that achieves both simplicity and effectiveness. The composite design of M+1 shift registers with specific connection patterns creates a system that maintains low device complexity while providing robust error correction capability through the collective operation of multiple simple components.
Data Source
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AI summary
An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes) is disclosed. The encoder exhibits encoding rates realized with a small circuit-scale and a high data reception quality. In the encoder (200), an encoding rate setting unit (250) sets an encoding rate (s-1)/s (s=z), and an information creating unit (210) sets information including from information Xs,i to information Xz-1,i to zero. A first information computing unit (220-1) receives information X1,i at time point i to compute the X1(D) term of formula (1). A second information computing unit (220-2) receives information X2,i at time point i to compute the X2(D) term of formula (1). A third information computing unit (220-3) receives information X3,i at time point i to compute the X3(D) term of formula (1). A parity computing unit (230) receives parity Pi-1 at time point i-1 to compute the P(D) of formula (1). The exclusive OR of the results of the computation is obtained as parity Pi at time i. Ax.