LDPC Error Correction Circuit With Selective Check Node Activation

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Solution Overview

Problem

Current error correction circuits based on low density parity check (LDPC) codes face inefficiencies in power consumption and performance due to the need for continuous operation of all check node units, which is not optimized for varying error rates in data transmission and storage.

Innovation Solution

An error correction circuit that includes a decoder with check node units and variable node units, a syndrome check circuit to calculate a reference value for error rates, and a control circuit to selectively power off check node units based on the error rate, using a parity check sub-matrix with reduced rows to decrease power consumption while maintaining decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all check node units are continuously operated to ensure decoding performance, then error correction reliability is maintained, but power consumption increases

Engineering Contradiction:

Improveerror correction performanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the operation state of check node units changeable based on error rate conditions. The control circuit dynamically adjusts which check node units are active versus powered off according to the syndrome check results, transitioning between different operational states to optimize the balance between reliability and power consumption.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies local quality by differentiating the operational status of individual check node units rather than treating them uniformly. Based on the syndrome check, the control circuit selectively activates only the necessary check node units (those corresponding to non-zero syndrome bits) while powering off others, giving different functional qualities to different parts of the system based on actual error conditions.

Inventive Principle:

Principle #3Local quality

2Reliability

If power is supplied to all check node units to handle high error rates, then decoding reliability is improved, but power consumption increases unnecessarily during low error rates

Engineering Contradiction:

Improvedecoding reliabilityVSAvoidunnecessary power consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies feedback by using the syndrome check circuit to continuously monitor the error state of the codeword and feed this information back to the control circuit. The control circuit then adjusts the power supply state of check node units based on this feedback, creating a closed-loop system that adapts power consumption to actual error conditions rather than operating in a fixed state.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent applies parameter changes by altering the operational parameter (power supply state) of check node units based on the error rate parameter. When the syndrome check indicates low error rates, the system changes the power supply parameter to reduce consumption; when errors are detected, it changes back to maintain reliability, dynamically adjusting parameters based on system conditions.

Inventive Principle:

Principle #35Parameter changes

3Loss of energy

If check node units are powered off to reduce power consumption, then energy efficiency is improved, but decoding performance may deteriorate

Engineering Contradiction:

Improvepower consumption reductionVSAvoiddecoding performance

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies partial action by activating only the necessary subset of check node units required to correct the detected errors rather than operating all units. The syndrome check identifies exactly which check nodes are needed (those corresponding to non-zero syndrome bits), and the system applies power and computational resources only to these partial units, avoiding excessive action on unnecessary nodes.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS10606695B2Error correction circuit and memory system including the same

Publication Date: 2020.03.31 SK HYNIX INC

AI summary

An error correction circuit includes a decoder including a plurality of check node units and variable node units corresponding to a parity check matrix of low density parity check (LDPC) scheme, and configured to generate decoded data by decoding a codeword; a syndrome check circuit configured to calculate a reference value for the codeword based on the parity check matrix, and generate a decoder operation control signal corresponding to the reference value; and a control circuit configured to control whether to operate each of the plurality of check node units and variable node units of the decoder in response to the decoder operation control signal, wherein the decoder decodes the codeword based on check node units and variable node units which operate according to the control of the control circuit among the plurality of check node units and variable node units.