Non-Binary LDPC Check Node Architecture for Lower-Latency Decoding
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Solution Overview
Problem
Current architectures for check node processing units in iterative decoders, particularly in non-binary LDPC codes, face high computational complexity and latency issues, limiting their efficiency and adaptability in decoding signals.
Innovation Solution
The proposed solution involves a decoder architecture with check node processing units divided into blocks of sub-check nodes, utilizing block division parameters to compute syndromes in parallel, and employing a combination of syndrome-based and forward-backward architectures to reduce computational complexity and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional check node processing architectures are used in non-binary LDPC decoders, then decoding accuracy can be maintained, but computational complexity and latency increase significantly
Solution Approach 1:
The check node processing unit is divided into multiple sub-check node processing units, each handling a subset of variable node messages. This segmentation reduces the computational burden on each individual unit while maintaining overall decoding accuracy through coordinated processing across all sub-units.
Solution Approach 2:
The patent introduces a new architectural dimension by combining syndrome-based processing and forward-backward processing in parallel paths. This dimensional expansion allows the system to achieve both accuracy and efficiency by leveraging the strengths of different processing approaches simultaneously.
2Measurement precision
If traditional check node processing architectures are used in non-binary LDPC decoders, then decoding accuracy can be maintained, but latency increases
Solution Approach 1:
By segmenting the check node processing into parallel sub-units, each sub-unit can process messages independently and simultaneously, reducing the overall processing time and latency while maintaining decoding accuracy through the coordinated output of all sub-units.
Solution Approach 2:
The syndrome-based processing path performs preliminary computations on variable node messages before the forward-backward processing stage. This preliminary action prepares data in advance, reducing the computational workload and latency in subsequent processing stages.
3Productivity
If complex check node processing architectures are implemented, then decoding performance can be improved, but hardware implementation cost increases
Solution Approach 1:
The check node processing unit is divided into multiple sub-check node processing units, each with simplified individual hardware requirements. This segmentation allows for more efficient hardware utilization and reduces overall implementation cost while maintaining high decoding performance through parallel processing.
Solution Approach 2:
The hybrid architecture integrates both syndrome-based and forward-backward processing capabilities within a unified check node processing framework. This multi-functionality allows the hardware to achieve high decoding performance without requiring completely separate processing systems, thereby reducing overall hardware cost.
Data Source
AI summary
Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to:determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; anddetermine at least one check node message from at least one syndrome.