LDPC Decoder Check Node Gating for Lower-Power Iterative Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current LDPC decoders face high power consumption due to redundant operations during the iterative decoding process, with approximately 40% of efforts being unnecessary for convergence, which does not contribute to error correction performance.
Innovation Solution
Implementing a check node convergence tester to disable redundant operations by determining when check nodes have converged, thereby reducing power consumption and processing efforts, and using adaptive control to skip or gate off unnecessary processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative decoding operations are performed continuously until convergence, then error correction performance is improved, but power consumption increases due to redundant operations
Solution Approach 1:
The patent applies partial action by performing decoding operations only on check nodes that have not yet converged. The convergence tester identifies which check nodes require further processing, and the decoder selectively applies decoding operations only to those nodes, avoiding redundant operations on already-converged nodes. This reduces power consumption while maintaining error correction performance.
Solution Approach 2:
The patent implements feedback through a convergence tester that continuously monitors the state of check nodes during the iterative decoding process. The tester provides feedback information about which check nodes have converged and which require further processing, allowing the decoder to adaptively adjust its operations and avoid redundant computations.
2Reliability
If all decoding operations are performed in each iteration, then convergence is ensured, but processing time increases due to redundant operations
Solution Approach 1:
The patent performs partial decoding operations only on check nodes that have not converged, as identified by the convergence tester. This selective approach reduces the number of processing steps required in each iteration while ensuring that all necessary decoding operations are eventually performed, maintaining convergence assurance with reduced processing time.
Solution Approach 2:
The patent segments the decoding process by dividing check nodes into two groups: those that have converged and those that have not. The convergence tester enables this segmentation by identifying the state of each check node, allowing the decoder to process only the relevant segment (non-converged nodes) in each iteration, thereby reducing overall processing time.
3Productivity
If layer processors operate in parallel for all check nodes, then decoding speed is improved, but power consumption increases due to redundant parallel operations
Solution Approach 1:
The patent applies partial action to parallel processing by enabling layer processors to operate in parallel only on check nodes that require processing, as identified by the convergence tester. This selective parallel operation maintains high decoding speed while reducing power consumption by avoiding redundant parallel operations on already-converged check nodes.
Solution Approach 2:
The patent introduces dynamics to the parallel processing architecture by making the operation of layer processors adaptive based on the convergence state of check nodes. The convergence tester dynamically controls which layer processors are active in each iteration, allowing the system to optimize the balance between decoding speed and power consumption based on real-time decoding progress.
Data Source
AI summary
A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.