Layered LDPC Decoding with Parallel Check Node Updates
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Solution Overview
Problem
Existing LDPC code decoders are inflexible and inefficient, as they can only decode specific types of LDPC codes, and implementing high-performance LDPC code decoders in hardware is challenging due to the tradeoff between code irregularity and hardware efficiency.
Innovation Solution
A layered decoding architecture for LDPC codes that uses multiple parity check update modules, adder modules, and a cyclic shift or permuter module to process data blocks in parallel, allowing for the decoding of various LDPC codes by updating check node values and probability estimates, and rearranging data to improve decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple LDPC code types are supported, then adaptability is improved, but device complexity increases
Solution Approach 1:
The decoder is designed with a universal architecture that can decode multiple types of LDPC codes (regular, irregular, quasi-cyclic, non-quasi-cyclic) using the same hardware structure. The parity check update modules and adder modules are configured to handle different code types through flexible data routing and processing sequences, eliminating the need for separate dedicated decoders for each code type.
Solution Approach 2:
The decoder employs dynamic configuration capabilities where the processing order and data flow can be adjusted based on the specific LDPC code type being decoded. The system can dynamically reconfigure the operation sequence of parity check update modules and adder modules to match the requirements of different code structures, enabling adaptability without permanent hardware changes.
2Productivity
If parallel processing is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The decoding process is segmented into distinct functional stages: probability value estimation, extrinsic estimate calculation, and check node value updating. Multiple adder modules and parity check update modules operate in parallel on different segments of the data, enabling simultaneous processing of multiple data blocks while maintaining manageable module complexity through clear functional separation.
Solution Approach 2:
The architecture merges the functions of multiple processing elements into a coordinated system where adder modules and parity check update modules work together in a unified processing pipeline. This merging allows parallel processing of multiple LDPC code types within a single integrated decoder structure, achieving high productivity without proportionally increasing overall device complexity.
Data Source
AI summary
A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix. The system also comprises a plurality of parity check update modules (PCUMs) in parallel with each other, coupled to the first adder module and adapted to update the check node value estimate, and a second adder module coupled to the plurality of PCUMs and adapted to update the probability value estimate using the extrinsic estimate and the updated check node value estimate. The PCUMs process at least some columns of at least some rows of the parity check matrix in a serial fashion.