LDPC Check Node Update Using Approximate Minima
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The implementation of low density parity check (LDPC) code decoders is hindered by high hardware complexity, particularly in the check node updating process, which leads to increased resource consumption and potential performance degradation, despite their superior error correction capabilities.
Innovation Solution
The proposed solution involves a check node update processor that uses an AFM condition check unit to determine whether a specific condition is satisfied, setting an approximate minimum value for check node outputs when the condition is met, and calculating a true minimum value otherwise, thereby reducing hardware complexity and resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the belief propagation (sum-product) method is used for LDPC decoding, then error correction capability is improved, but hardware complexity increases significantly
Solution Approach 1:
The patent replaces the complex sum-product algorithm with the min-sum algorithm, which uses simpler operations (comparators, MUX, adder) instead of complex product and tanh operations. This substitutes a computationally expensive method with a cheaper alternative that achieves comparable error correction performance with significantly reduced hardware complexity
Solution Approach 2:
The patent introduces normalization factors and offset values as adjustable parameters to compensate for the approximation errors in the min-sum algorithm. By optimizing these parameters, the error correction performance approaches that of the sum-product method while maintaining the hardware efficiency of min-sum operations
2Reliability
If the check node degree increases to improve error correction, then decoding performance is improved, but hardware resources increase proportionally
Solution Approach 1:
The patent divides the check node processing into multiple parallel processing units, where each unit handles a subset of variable nodes. This segmentation allows the system to process higher degree check nodes by distributing the computational load across multiple simpler units rather than requiring a single complex unit, thus managing hardware resources more efficiently
Solution Approach 2:
The patent performs a limited number of decoding iterations rather than exhaustive iterations, achieving sufficient error correction performance with fewer computational cycles. This partial action approach reduces the total hardware resource consumption while maintaining acceptable decoding performance
3Device complexity
If the implementation area of the decoder is reduced to save hardware resources, then resource consumption is reduced, but error correction capability degrades
Solution Approach 1:
The patent replaces the belief propagation mechanism with the min-sum mechanism, substituting a mathematically rigorous but hardware-intensive approach with a simplified approximation that uses basic logical operations. This substitution reduces implementation area while preserving sufficient error correction capability for practical applications
Data Source
AI summary
A check node update processor of the low density parity check (LDPC) code decoder includes: an approximate first minimum (AFM) condition check unit which checks whether a predetermined specific condition is satisfied, and a check node determining unit which sets an approximate minimum value as a size of an entire check node output when it is determined that the specific condition is satisfied as a checking result in the AFM condition check unit and calculates a first minimum value as a true minimum value and sets a second minimum value as an approximate minimum value when it is determined that the specific condition is not satisfied to determine a size of the check node output.