Non-Binary LDPC Check Node Sorting With FIFO Insertion Logic
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Solution Overview
Problem
Existing architectures for elementary check node processors in non-binary LDPC code decoders face high computational complexity and latency due to the complexity of sorting and redundancy elimination operations, particularly when dealing with a large number of combinations of components in message passing algorithms.
Innovation Solution
A sorting device and method that utilize a plurality of FIFO memories and multiplexers to iteratively determine elementary check node components by selecting the most reliable symbols, reducing complexity and latency by sorting auxiliary components based on reliability metrics and performing control actions to update candidate components, thereby simplifying the sorting operation and reducing critical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sorting and redundancy elimination operations are used in elementary check node processors, then decoding accuracy is maintained, but computational complexity and latency increase significantly
Solution Approach 1:
The patent segments the sorting operation into multiple passes, where each pass processes a subset of auxiliary components. Instead of sorting all components at once, the system divides them into groups, sorts each group separately, and combines results. This segmentation reduces the complexity of each individual sorting operation while maintaining overall decoding accuracy through multiple refinement passes.
Solution Approach 2:
The patent applies preliminary filtering and coarse sorting before the final sorting operation. By pre-processing auxiliary components to eliminate obviously redundant or low-value candidates early in the process, the system reduces the number of components that require full sorting treatment, thereby reducing computational complexity while preserving the most reliable decoding information.
2Reliability
If comprehensive sorting of auxiliary components is performed, then decoding reliability is improved, but processing latency increases
Solution Approach 1:
The patent implements partial sorting where only a sufficient number of top-ranked auxiliary components are fully sorted, rather than sorting all components exhaustively. By identifying and processing only the most promising candidates (partial action), the system achieves adequate decoding reliability without the full time cost of comprehensive sorting, thus reducing processing latency while maintaining acceptable performance.
Solution Approach 2:
The sorting process is divided into multiple time-staggered passes, where different sets of auxiliary components are sorted in sequence rather than all simultaneously. This segmentation allows the system to spread computational work over time, reducing peak latency while still achieving thorough sorting of critical components across multiple passes.
3Reliability
If the number of auxiliary components is increased to improve decoding performance, then error correction capability is enhanced, but computational complexity and critical path length increase
Solution Approach 1:
The patent applies preliminary filtering to reduce the set of auxiliary components before they enter the full sorting and processing pipeline. By pre-identifying and eliminating components that are unlikely to contribute significantly to decoding accuracy, the system can work with a reduced set of components, thereby maintaining error correction capability while reducing the critical path length and computational complexity of subsequent operations.
Solution Approach 2:
The patent processes only a selected subset of auxiliary components through the complete sorting and decoding pipeline, rather than processing all generated auxiliary components. By applying partial action to only the most promising candidates, the system achieves adequate error correction performance without the full computational burden and critical path delays that would result from processing every auxiliary component.
Data Source
AI summary
A sorting device and method for determining elementary check node components in an elementary check node processor implemented in a non-binary error correcting code decoder by sorting auxiliary components are presented. The auxiliary components are stored in a plurality of FIFO memories, each FIFO memory being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory. The sorting device is configured to sort the auxiliary components by a plurality of multiplexers arranged sequentially. Each multiplexer is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the illustrated receiving, updating and sorting steps.