LDPC Decoder Check Node Storage for Lower Gate Count
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Solution Overview
Problem
Traditional LDPC decoder architectures have a high footprint due to the need for flip flops to store check nodes, which are expensive in terms of gate count and silicon area, especially as codeword lengths increase, leading to prohibitively high gate counts and power consumption.
Innovation Solution
A check node storage (CNS) architecture that dynamically swaps check nodes between latching circuitry and volatile memory, storing active nodes in flip flops and inactive nodes in SRAM, reducing the overall gate count and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If check nodes are stored in flip flops to ensure availability at every clock cycle, then decoding reliability is improved, but decoder footprint and gate count increase significantly
Solution Approach 1:
The patent implements a dynamic check node storage architecture where check nodes are selectively stored in flip flops during active decoding cycles and transferred to SRAM during inactive cycles. This dynamic approach allows the system to maintain decoding reliability when needed while reducing the decoder footprint by utilizing slower but area-efficient SRAM storage during non-active periods.
Solution Approach 2:
The patent employs periodic transfer of check nodes between flip flop and SRAM storage, synchronized with the decoding cycle. During active decoding phases, check nodes reside in flip flops for rapid access, while during inactive phases, they are periodically transferred to SRAM. This periodic action maintains reliability during critical operations while reducing overall area requirements.
2Area of stationary object
If check nodes are stored in SRAM to reduce gate count, then decoder footprint is reduced, but access speed becomes insufficient for practical decoding
Solution Approach 1:
The system dynamically switches storage locations based on operational requirements. SRAM is used for area-efficient storage during inactive periods, while flip flops provide high-speed access during active decoding cycles. This dynamic switching resolves the speed-area tradeoff by utilizing each storage type only when its characteristics are needed.
Solution Approach 2:
The patent introduces a controller as an intermediary that manages data transfer between SRAM and flip flops. This controller coordinates the periodic transfer of check nodes, ensuring that high-speed flip flop access is available when needed while utilizing area-efficient SRAM storage during inactive periods, thus bridging the speed and area requirements.
3Reliability
If codeword length is increased to improve decoding performance, then error correction capability is improved, but gate count and power consumption become prohibitively high
Solution Approach 1:
The dynamic storage architecture enables the decoder to handle longer codewords by reducing the number of flip flops required. Check nodes for longer codes are stored in SRAM during inactive cycles, allowing the system to scale to longer codeword lengths without proportionally increasing flip flop count and associated gate complexity.
Solution Approach 2:
The patent changes the storage parameter from exclusively using flip flops to a hybrid SRAM-flip flop architecture. This parameter change reduces the gate count for storing check nodes, enabling the implementation of longer codewords with improved error correction capability while keeping power consumption and device complexity within acceptable limits.
Data Source
AI summary
A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.