LDPC Channel Interleaving by Check-Node Degree for 64QAM
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Solution Overview
Problem
Current communication systems using Low Density Parity Check (LDPC) codes lack a detailed scheme for channel interleaving/deinterleaving, which is essential for maximizing coding performance, especially in high-order modulation scenarios like 16QAM and 64QAM, and do not adequately account for the performance differences between high- and low-protected initial messages and the degree of check nodes.
Innovation Solution
A channel interleaving/deinterleaving apparatus and method that designs interleaving based on the performance difference between high- and low-protected initial messages and the degree of check nodes in LDPC codes, using specific rules to allocate bits to variable nodes with varying error correction capabilities, thereby optimizing error correction capabilities in communication systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel interleaving is not performed according to LDPC code characteristics, then device complexity is reduced, but error correction performance deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the interleaving scheme based on the degree of check nodes. Specifically, variable nodes connected to check nodes with degree less than a threshold value are interleaved differently from those connected to check nodes with degree greater than or equal to the threshold. This localized differentiation optimizes error correction performance for different node types without requiring a completely complex interleaving structure throughout the entire system.
2Reliability
If bits are uniformly allocated to variable nodes, then device complexity is reduced, but error correction capability deteriorates
Solution Approach 1:
The patent implements local quality in bit allocation by assigning different numbers of bits to different variable nodes based on their connection characteristics. Variable nodes connected to check nodes with lower degree receive a different number of bits compared to variable nodes connected to check nodes with higher degree. This non-uniform allocation optimizes the error correction capability by matching bit allocation to the specific needs of each variable node, rather than applying a uniform scheme across all nodes.
3Adaptability or versatility
If conventional interleaving schemes are used for high-order modulation, then adaptability is reduced, but manufacturing precision is improved
Solution Approach 1:
The patent applies dynamics by making the interleaving scheme adaptive to different modulation types. The system dynamically adjusts the interleaving parameters and bit allocation based on whether high-order modulation (such as 16QAM or 64QAM) is being used. This dynamic adaptation allows the same LDPC code structure to maintain optimal performance across different modulation schemes, rather than requiring fixed interleaving parameters that would only be optimized for one specific modulation type.
Data Source
AI summary
A channel interleaving method and apparatus in a communication system using a low density parity check (LDPC) code. Upon receipt of information data bits, an encoder encodes the information data bits into an LDPC codeword using a predetermined coding scheme. A channel interleaver interleaves the LDPC codeword according to a predetermined channel interleaving rule. A modulator modulates the channel-interleaved LDPC codeword into a modulation symbol using a predetermined modulation scheme.