LDPC Decoder Check-Node Scheduling for False Convergence Control
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Solution Overview
Problem
Current LDPC decoders face inefficiencies in convergence due to sequential processing of check nodes and bit nodes, are ineffective in handling abnormal conditions like oscillating bit errors, and struggle with varying iteration requirements for decoding frames, leading to potential data loss or bit errors.
Innovation Solution
The method involves processing groups of check nodes in parallel, updating bit nodes sooner within an iteration, and using a novel memory configuration for efficient message storage and processing, along with mechanisms to detect and handle abnormal conditions by tracking unresolved parity check equations and applying a 'nudge' algorithm to ensure convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If check nodes and bit nodes are processed sequentially in traditional LDPC decoders, then the decoding process is simpler to implement, but the convergence time increases significantly
Solution Approach 1:
The decoder architecture is segmented into multiple independent processing units, each capable of processing check nodes and bit nodes simultaneously. The check node processing unit and bit node processing unit are separated into distinct functional blocks that can operate in parallel, thereby increasing decoding speed without significantly increasing overall system complexity.
Solution Approach 2:
The patent introduces a temporal dimension to the processing by allowing overlapping execution of check node processing and bit node processing within the same iteration. This dimensional change enables the decoder to perform operations that were previously sequential in a pipelined manner, effectively increasing productivity while maintaining manageable complexity.
2Productivity
If the decoder uses a fixed number of iterations based on average performance, then the decoding process is more predictable and easier to control, but frames requiring more iterations cannot be decoded correctly
Solution Approach 1:
The decoder dynamically adjusts the number of iterations based on the specific frame being decoded. Rather than using a fixed iteration count, the system monitors convergence criteria and adapts the iteration number in real-time, allowing frames that require more iterations to be decoded accurately while maintaining high throughput for frames that converge quickly.
Solution Approach 2:
The patent implements feedback mechanisms where the decoder monitors the convergence status of each frame during decoding. Based on this feedback, the system can determine whether to continue iterating or terminate early, thereby optimizing the balance between throughput and accuracy for different frame types.
3Device complexity
If the decoder processes all check nodes before updating bit nodes, then the processing logic is simpler, but the convergence rate decreases
Solution Approach 1:
The patent applies preliminary action by updating bit node values intermediate during check node processing rather than waiting for all check nodes to complete. This allows subsequent check nodes to benefit from updated bit node information, accelerating convergence without significantly complicating the processing logic.
Solution Approach 2:
The decoder maintains continuous useful action by overlapping check node processing with bit node updates within the same iteration. Rather than completing all check node processing before updating bit nodes, the system continuously performs both operations in an interleaved manner, reducing convergence time while keeping processing logic manageable.
Data Source
AI summary
An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing. The decoder may also employ a novel method for generating check node to bit node messages through a prescribed series of pair-wise computations.