LDPC Check-Node Hard Limiting for Low-SNR Error Floor Mitigation
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Solution Overview
Problem
Existing LDPC decoders face challenges in achieving desired performance, particularly at lower signal-to-noise ratios, and often result in error floors when used with higher order modulations such as 8-PSK, 16-APSK, and 32-APSK, due to inefficiencies in message passing and quantization.
Innovation Solution
The implementation of a decoder that partially hard-limits messages from check nodes, assigning maximum positive and negative values to messages above or below specified limits, and using optimized bit-to-symbol mappings, along with iterative message passing on a bipartite graph, to improve decoding performance and reduce error floors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard iterative message passing is used in LDPC decoders, then decoding complexity is manageable, but error floors occur at lower signal-to-noise ratios when used with higher order modulations
Solution Approach 1:
The patent applies parameter changes by modifying the message passing values during decoding. Specifically, it transforms soft decision values into hard decisions at check nodes and regenerates soft decisions with adjusted parameters (sign from check node message, magnitude from variable node message). This parameter transformation resolves the error floor issue while maintaining decoding complexity.
Solution Approach 2:
The patent inverts the traditional message passing approach by performing hard limiting at check nodes instead of variable nodes, and then regenerating soft decisions. This inversion of the decision-making process at different node types eliminates trapping sets that cause error floors in conventional decoders.
2Productivity
If higher order modulations (8-PSK, 16-APSK, 32-APSK) are used to increase data rate, then bandwidth efficiency improves, but error floors appear at lower signal-to-noise ratios
Solution Approach 1:
The patent changes the parameter representation of messages by converting between soft and hard decisions at different stages. This parameter transformation allows the decoder to handle higher order modulations more robustly by eliminating the error floors that normally appear at lower signal-to-noise ratios, thus maintaining reliability while supporting high data rates.
3Measurement precision
If soft decision values are used throughout the decoding process, then decoding accuracy is maintained, but trapping sets cause error floors
Solution Approach 1:
The patent inverts the conventional approach by applying hard limiting at check nodes rather than variable nodes, then regenerating soft decisions. This inverted approach disrupts the formation of trapping sets that cause error floors, while the regeneration of soft decisions preserves decoding accuracy for non-trapping-set cases.
Solution Approach 2:
The patent segments the message passing process into distinct hard decision and soft decision phases at different node types. By separating these functions spatially (hard at check nodes, soft at variable nodes) and temporally (alternating iterations), it maintains accuracy while avoiding error floors.
Data Source
AI summary
A digital communication decoding method for low-density parity-check coded messages. The decoding method decodes the low-density parity-check coded messages within a bipartite graph having check nodes and variable nodes. Messages from check nodes are partially hard limited, so that every message which would otherwise have a magnitude at or above a certain level is re-assigned to a maximum magnitude.