LDPC Encoding and Decoding Circuit With Fixed Interconnections
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Solution Overview
Problem
Conventional LDPC encoders and decoders are complex and inefficient due to the need for complicated control logic and large routing networks, which hinder their performance in data transmission systems.
Innovation Solution
A decoding and encoding circuit design that employs a data buffer with storage elements and a processing circuit, where the association of storage elements with inputs and outputs is determined by fixed decoding or encoding parameters, allowing for hard-wired interconnections and resource sharing between encoder and decoder, facilitating efficient processing and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional LDPC encoders and decoders are used with complicated control logic and large routing networks, then the decoding functionality is achieved, but the device complexity increases and processing efficiency decreases
Solution Approach 1:
The patent applies universality by designing a single processing circuit that can function as both an encoder and a decoder. The same processing circuit is used for both encoding operations (generating parity bits from information bits) and decoding operations (processing received signals through iterative decoding). This eliminates the need for separate encoder and decoder circuits, reducing overall device complexity while maintaining full encoding and decoding functionality.
Solution Approach 2:
The patent merges the encoder and decoder into a unified architecture. The processing circuit integrates both encoding logic and decoding logic, with the same hardware resources being time-shared or context-switched between encoding and decoding modes. This merging reduces the total number of components, simplifies control logic, and improves resource utilization efficiency.
2Device complexity
If conventional LDPC encoders and decoders are used with large routing networks, then the decoding functionality is achieved, but the device complexity and area increase
Solution Approach 1:
The processing circuit serves multiple functions including encoding, decoding, and intermediate signal processing. By making the processing circuit universal, the patent eliminates the need for dedicated routing networks that would connect separate encoder and decoder blocks. The same processing resources handle all signal transformations, reducing routing network complexity and circuit area.
Solution Approach 2:
The patent extracts and eliminates the complex routing network from the conventional architecture. By integrating encoding and decoding functions into a single processing circuit, the patent removes the need for extensive inter-connect routing between separate encoder and decoder modules, thereby reducing circuit area and simplifying the overall design.
3Reliability
If conventional LDPC encoders and decoders are used, then the decoding functionality is achieved, but the number of components and overall system complexity increase
Solution Approach 1:
The patent implements a universal processing circuit that performs both encoding and decoding operations. This single circuit replaces what would traditionally require separate encoder and decoder components, reducing the total number of components while maintaining full decoding functionality. The processing circuit adapts its operation based on the input data and control signals, ensuring reliable decoding performance.
Data Source
AI summary
A decoding circuit including a data buffer comprises a plurality of storage elements for storing data symbols, a processing circuit comprising a plurality of inputs and outputs, wherein the processing circuitry is configured to process data symbols received via the plurality of inputs and outputs. First and second decoding parameters are determined by a decoding rule and wherein the first and the second decoding parameters are not changed throughout the decoding process.