LDPC Decoder Layout Using CNU Arrays and Incremental Shifts
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Solution Overview
Problem
Low density parity check (LDPC) decoders face complexity in interconnect issues and require significant computational resources, limiting their efficiency in error correction for next-generation communication and data storage systems.
Innovation Solution
The proposed solution involves a novel LDPC decoder design that reduces message storage memory and routing logic by using a check node unit (CNU) with comparators to determine minimum values and a method for incremental shifts in check node processing, allowing for block parallel processing and cyclic shifts without active routers, thereby simplifying the architecture and reducing computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional LDPC decoder design is used, then error correction performance is achieved near the Shannon limit, but device complexity and interconnect issues increase
Solution Approach 1:
The LDPC decoder is segmented into multiple check node unit (CNU) arrays, where each array processes a specific block row of the parity check matrix. This segmentation allows parallel processing while reducing interconnect complexity within each array.
Solution Approach 2:
The patent introduces incremental shifts in the check node processing along a new dimension, allowing cyclic shifts to be performed without active routers by utilizing the incremental shift characteristic of the blocks in the layer.
2Measurement precision
If more computational resources are allocated to the LDPC decoder, then decoding accuracy improves, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent uses simplified comparator circuits that copy and compare stored minimum values with received variable messages, reducing the need for complex computational resources while maintaining decoding accuracy through iterative processing.
Solution Approach 2:
The patent changes the operational parameters of the check node units by using incremental shifts and simplified comparison operations instead of full computational processing, reducing manufacturing complexity while preserving decoding performance.
3Device complexity
If message storage memory is reduced, then device complexity decreases, but decoding reliability may be compromised
Solution Approach 1:
The patent performs preliminary actions by pre-storing minimum values in the check node units and using incremental shifts to track changes, reducing the need for extensive message storage memory while maintaining decoding reliability through the preserved minimum value information.
4Productivity
If parallel processing is implemented, then productivity increases, but interconnect complexity and routing logic increase
Solution Approach 1:
The decoder is divided into multiple CNU arrays that process different block rows in parallel, with each array handling its own incremental shifts independently, thus achieving parallel processing without requiring complex global routing logic.
Solution Approach 2:
Each check node unit array performs its own incremental shifts and processing autonomously without requiring active routers to manage data flow between units, allowing parallel processing while keeping routing logic simple through self-service operation.
Data Source
AI summary
A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.